Denis Flandre

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BibTeX - Flandre

Publications

Kashif Nawaz, Dina Heidar Kamel, François-Xavier Standaert, and Denis Flandre. Scaling Trends for Dual-Rail Logic Styles against Side-Channel Attacks: a Case-Study, Constructive Side-Channel Analysis and Secure Design - 8th International Workshop, COSADE 2017, Paris, France, April 13-14, 2017, Lecture Notes in Computer Science (LNCS), Springer, April 2017, to appear BibTeX

Dina Heidar Kamel, Guerric de Streel, Santos Merino Del Pozo, Kashif Nawaz, François-Xavier Standaert, Denis Flandre, and David Bol. Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers, In C. Carlet and A. Hasan and V. Saraswat, editor(s), Security, Privacy, and Applied Cryptography Engineering - 6th International Conference, SPACE 2016, Hyderabad, India, December 14-18, 2016, Proceedings, Lecture Notes in Computer Science, pages 233-248, Springer, December 2016, http://dx.doi.org/10.1007/978-3-319-49445-6_13 BibTeX

Cédric Hocquet, Dina Heidar Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, and François-Xavier Standaert. Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags, In Journal of Cryptographic Engineering, April 2011 BibTeX

Dina Heidar Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, and David Bol. Glitch-Induced Within-Die Variations of Dynamic Energy in Voltage-Scaled Nano-CMOS Circuits, proceedings of ESSCIRC 2010, September 2010 BibTeX

Dina Heidar Kamel, Mohamed Dessouky, and Denis Flandre. Enhanced performance of SERDES current-mode output driver using 0.13 μm PD SOI CMOS, SOI Conference, IEEE, October 2009 PDF BibTeX

Dina Heidar Kamel, David Bol, François-Xavier Standaert, and Denis Flandre. Comparison of Ultra-Low-Power and static CMOS full adders in 0.15 μm FD SOI CMOS, SOI Conference, IEEE, October 2009 PDF BibTeX

Dina Heidar Kamel, François-Xavier Standaert, and Denis Flandre. Scaling trends of the AES S-Box low power consumption in 130 and 65 nm CMOS technology nodes, ISCAS, IEEE Circuits and Systems Society, IEEE, May 2009 PDF BibTeX

Dina Heidar Kamel, David Bol, and Denis Flandre. Impact of Layout Style and Parasitic Capacitances in Full Adder, SOI Conference, IEEE, October 2008 PDF BibTeX

Ilham Hassoune, François Mace, Denis Flandre, and Jean-Didier Legat. Dynamic differential self-timed logic families for robust and low-power security ICs, In INTEGRATION, the VLSI Journal, Volume 40, pages 355-364, March 2007 BibTeX

Ilham Hassoune, François Mace, Denis Flandre, and Jean-Didier Legat. Low-swing current mode logic (LSCML): a new logic style for secure and robust smart cards against power analysis attacks., In Microelectronics Journal, Volume 37, pages 997-1006, May 2006 BibTeX

Amaury Neve, Denis Flandre, and Jean-Jacques Quisquater. Feasibility of Smart Cards in Silicon-On-Insulator (SOI) Technology, pages 1-7, May 1999 PDF BibTeX

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