@INPROCEEDINGS{cgUCL-BPST18,
 	AUTHOR={Bellizia, Davide and Palumbo, Gaetano and Scotti, Giuseppe and Trifiletti, Alessandro},
	TITLE={{A Novel Very Low Voltage Topology to implement MCML XOR Gates}},
	BOOKTITLE={ 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)},
	PUBLISHER={IEEE},
	MONTH={8},
	YEAR={2018},
}