Electronic Circuits and Systems

Figure : Architecture of a smart sensor node with the related challenges for a sustainable Internet-of-Things

The research direction in electronic circuits and systems at UCL spreads over all levels of abstraction in integrated circuit (IC) design: from nanoscale CMOS process technology to disruptive analog/digital/RF circuit building blocks to complex mixed-signal systems-on-chip (SoCs). An overview of current and latest research activities can be found in this presentation.

Principal Investigators :

David Bol, Denis FlandreJean-Didier Legat, François-Xavier Standaert

Research Areas :

Robust circuit design in emerging CMOS technologies both in More-Moore and More-than-Moore directions require accurate technology characterization and models. In the ECS group, a strong focus is put on analog/RF characterization of these emerging technologies as well as on research in digital design enablement and the study of new concepts related to on-chip sensors, actuators and energy harvesters.

Since 2000, the spectrum of electronic circuits systems is no longer divided into high-performance (high-speed, high accuracy, high robustness, etc.) and low-power applications. Indeed, energy efficiency is today paramount for all types of applications including high-performance computing, wireless communications, remote sensing, harsh-environment operation, power management, etc. In this context, research is carried out in the ECS group to improve the energy efficiency of various types of high-performance applications. Research at the circuit design abstraction level are focused on both analog and digital design methodologies, analog/mixed-signal (AMS) building blocks (RF, power management), digital architecture (DSP, memories) and adaptive techniques, sensing circuits (imagers, biosensors, ADC).

Securing small embedded devices against mathematical and physical attacks while maintaining the level of performances of emerging applications (sensor networks, RFIDs, Internet of Things) is a challenging optimization goal. It usually requires mixing advances at different abstraction levels (protocol, algorithmic, implementation). In this context, we investigate tracks to take advantage of advanced technologies in order to both reduce the implementation and energy cost, and the security of the chip against tampering attacks, fault attacks and side-channel attacks.

The Internet-of-Things (IoT) is progressively changing the way we live but its development triggers key technical challenges. IoT-related researches in the ECS group targets sustainability aspects of the IoT both technical and environmental, energy-harvesting operation (harvesters and power management) and ultra-low-power SoC design with experimental prototyping of SoCs including computing, sensing, wireless communication and power management.

Simulation and design tools are based on industry-standard softwares for integrated processes, devices and circuits. Prototyping is based on both cutting-edge CMOS manufacturing processes from industrial leaders (ST-Microelectronics, TSMC, UMC, X-Fab) and home-brewn processes for functionality diversification (“More than Moore”) supported by UCL WinFab facility. Circuits and systems characterizations are supported by UCL Welcome facility in a very large range of operating conditions (frequencies, temperatures, mechanical stress). Component irradiation for space, biomedical and nuclear physics related investigations is available at the nearby cyclotron research centre on benches qualified by ESA.

The design of custom ICs and SoCs is further investigated in collaboration with experts in the field of application of the circuits (e.g.: image processing, robotics, biomedical, smart sensors, aerospace, radiation hardness, nuclear science, high temperature, energy harvesting, green electronics, ultra low power, RFID, flexible electronics, telecommunication, RF, security, cryptography, etc).

Recent collaborations in electronics circuits and systems include: CEA-LETI (France), ST-Microelectronics (France), CNM (Spain), EADS (France), nSilition (Belgium), CISSOID (Belgium), Deltatec (Belgium), ACIC (Belgium), CETIC (Belgium), IMEC-Holst (Netherlands), AMS (Austria), MGL (Austria), Siemens (Germany), Samsung (UK), Fraunhofer (Germany), Thales (Belgium, France), SOI Industrial Consortium (USA), P.E. International (USA), Purdue University (USA).

Major recent projects (Funding, Topic) include : NanoSec (ARC, security), MSP (FP7, smart building), SAVE (RW, smart buildings/cities), CRASH (ERC, security), STARflo+ (RW, biomedical), TRIADE (FP7, aerospace), E-User (RW, RFID), EUROSOI+ (FP7, low-power SOI), MIMOCOM (RW, MIMO RF systems), S@T (RW, radiation hardness), Trappist (FNRS, nuclear physics), NANOTIC (RW, biochemical wireless sensors).

Most recent publications

Below are listed the 10 most recent journal articles and conference papers produced in this research area. You also can access all publications by following this link : see all publications.


Journal Articles


1. Gimeno Gasca, Cecilia; Bol, David; Flandre, Denis. Multilevel Half-Rate Detector for Clock and Data Recovery Circuits. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , p. 5 (2018). doi:10.1109/TVLSI.2018.2826440. http://hdl.handle.net/2078.1/199147

2. Aguirre, Javier; Bol, David; Flandre, Denis; Sanchez-Azqueta, Carlos; Celma, Santiago. A robust 10 Gbps duobinary transceiver in 0.13 μm SOI CMOS for short-haul optical networks. In: IEEE Transactions on Industrial Electronics, Vol. 99, p. 1 (2017). doi:10.1109/TIE.2017.2716870. http://hdl.handle.net/2078.1/191203

3. Doria, R.T.; Flandre, Denis; Trevisoli, R.; De Souza, Michelly; Pavanello, Marcello Antonio. Effect of the back bias on the analog performance of standard FD and UTBB transitors-based self-cascode Structures. In: Semiconductor Science and Technology, Vol. 32, p. 1 (2017). doi:10.1088/1361-6641/aa7659. http://hdl.handle.net/2078.1/191191

4. de Streel, Guerric; Stas, François; Gurné, Thibaut; Durant, François; Frenkel, Charlotte; Cathelin, Andreia; Bol, David. SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping. In: IEEE Journal of Solid State Circuits, Vol. 52, no.4, p. 1163-1177 (23/03/2017). doi:10.1109/JSSC.2016.2645607. http://hdl.handle.net/2078.1/189108

5. Poncelet, Olivier; Kotipalli, Raja Venkata Ratan; Vermang, Bart; Macleod, Angus; Francis, Laurent; Flandre, Denis. Optimisation of rear reflectance in ultra-thin CIGS solar cells towards >20% efficiency. In: Solar Energy, Vol. 146, p. 443-452 (01/03/2017). doi:10.1016/j.solener.2017.03.001. http://hdl.handle.net/2078.1/184794

6. Galembeck, Egon H.S.; Renaux, Christian; Flandre, Denis; Finco, Saulo; Gimenez, Salvador P. Boosting the SOI MOSFET Electrical Performance by Using the Octogonal Layout Style in High Temperature Environment. In: IEEE Transactions on Device and Materials Reliability, Vol. 17, no.1, p. 1-8 (03/2017). doi:10.1109/TDMR.2017.2652729. http://hdl.handle.net/2078.1/183152

7. Amor, Sedki; André, Nicolas; Gérard, Pierre; Ali, S.Z.; Udrea, F.; Tounsi, F.; Mezghani, B.; Francis, laurent; Flandre, Denis. Reliable characteristics and stabilization of on-membrane SOI MOSFET-based components heated up to 335 °C. In: Semiconductor Science and Technology, Vol. 32, no.1, p. 9 (19/12/2016). doi:10.1088/1361-6641/32/1/014001. http://hdl.handle.net/2078.1/181119

8. Novo, C.; Bühler, R.; Giacomini, R.; Afzalian, Aryan; Flandre, Denis. Quantum Efficiency Improvement of SOI PIN Lateral Diodes Operating as UV Detectors at High Temperatures. In: IEEE Sensors Journal, Vol. PP, no.99, p. 8 (04/01/2017). doi:10.1109/JSEN.2017.2647848. http://hdl.handle.net/2078.1/181109

9. Pereira, A.S.N.; de Streel, Guerric; Planes, N.; Haond, M.; Giacomini, R.; Flandre, Denis; Kilchytska, Valeriya. An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models. In: Solid-State Electronics, Vol. 128, p. 67-71 (15/10/2016). doi:10.1016/j.sse.2016.10.017. http://hdl.handle.net/2078.1/181095

10. Friedt, J.-M.; Francis, Laurent. Combined surface acoustic wave and surface plasmon resonance measurement of collagen and fibrinogen layer physical properties. In: Sensing and Bio-Sensing Research, Vol. 11, p. 60-70 (25/05/2016). doi:10.1016/j.sbsr.2016.05.007. http://hdl.handle.net/2078.1/182370


Conference Papers


1. Gimeno Gasca, Cecilia; Flandre, Denis; Bol, David. Low-Power Half-Rate Dual-Loop Clock-Recovery System in 28-nm FDSOI. http://hdl.handle.net/2078.1/196445

2. Royo, C.; Sanchez-Azqueta, C.; Aldea, C.; Celma, C.; Gimeno Gasca, Cecilia. high-Linear Transimpedance Amplifier for Remote Antenna Units. http://hdl.handle.net/2078.1/196444

3. Haine, Thomas; Segers, Johan; Flandre, Denis; Bol, David. Gradient Importance Sampling: an Efficient Statistical Extraction methodology of High-Sigma SRAM Dynamic Characteristics. In: 2018 Design, Automation Test in Europe Conference Exhibition (PROCEEDINGS), 2018, 195-200. doi:10.23919/DATE.2018.8342002. http://hdl.handle.net/2078.1/191730

4. Peruzzi, Vinicius Vono; Renaux, Christian; Flandre, Denis; Gimenez, Salvador Pinillos. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style. http://hdl.handle.net/2078.1/197229

5. Gimeno Gasca, Cecilia; Bol, David; Flandre, Denis. SOI, from Basics to Applications. http://hdl.handle.net/2078.1/197198

6. Van Brandt, Léopold; Kilchytska, Valeriya; Raskin, Jean-Pierre; Parvais, Bertrand; Flandre, Denis. Optimal measurement parameters for accurate time-domain and spectral analyses of RTN. http://hdl.handle.net/2078.1/196450

7. Flandre, Denis; André, Nicolas; Al Kadi Jazairli, Mohamad; Olbrechts, Benoit; Gilet, Samuel; Haddad, Pierre-Antoine; Gimeno Gasca, Cecilia; Raskin, Jean-Pierre. vers des capteurs implantés de quelques mm³ à consommation ultra faible, avec transmissions de puissance en RF et de données en UWB. http://hdl.handle.net/2078.1/192482

8. Flandre, Denis; Kilchytska, Valeriya; Gimeno Gasca, Cecilia; Bol, David; Kazemi Esfeh, Babak; Raskin, Jean-Pierre. Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers. http://hdl.handle.net/2078.1/192479

9. Mesquida, Thomas; Valentian, Alexandre; Bol, David; beigne, Edith. Architecture Exploration of a Fixed Point Computation Unit using Precise Timing Spiking Neurons. In: Proceedings of the 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017), 2017, p. 8. http://hdl.handle.net/2078.1/191119

10. Stas, François; Bol, David. Integration of Level Shifting in a TSPC Flip-Flop for Low-Power Robust Timing Closure in Dual-Vdd ULV Circuits. http://hdl.handle.net/2078.1/189103