Teacher(s)
Language
English
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Main themes
Combinational logic circuits and sequential logic design. Digital building blocks (ALU, registers, ...).Hardware description language (SystemVerilog). Microarchitecture of a 32-bit RISC processor (single-cycle processor, multicyle processor and pipelined processor). Embedded processor architecture and I/O systems.
Learning outcomes
At the end of this learning unit, the student is able to : | |
In consideration of the reference table AA of the program "master in electrical engineering ", this course contributes to the development, to the acquisition and to the evaluation of the following experiences of learning:
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Content
- Combinational logic
- Sequential logic
- Design of digital circuits
- Simulation language and Verilog synthesis
- Main logic circuits: arithmetic circuits, memories, programmable circuits
- Architecture and microarchitecture of the ARM processor
- Memories (caches, ...)
- Peripherals and main communication systems
- Integration of digital systems (processor + dedicated hardware accelerator)
Teaching methods
The complete course is divided into 4 main parts, including a course-long project:
- PART 1: concepts of digital design and introduction to design tools. Project choice.
- PART 2: basic processor architectures. Design of your first hardware accelerator for the project.
- PART 3: advanced processor architectures. Design and simulation of hardware processors.
- PART 4: Outlook (sustainability in processor design) and final project work (integration of s aystem with a processor and associated task-specific accelerator)
Evaluation methods
The evaluation is based on three complementary assignments, worth 60 points in total:
It should be noted that, if the student and the teacher agree beforehand via Email, the examination of the second session can be done as an oral exam instead of a written one.
- A midterm evaluation (30 points), carried out mid-semester, containing:
- A theoretical part (on paper) - 15 points
- A practical part (on computers) - 15 points
- The project evaluation (30 points), composed of:
- A small intermediate project report (to be given before the smart week) - 5 points
- A final project report (to be given the last week of the course) - 10 points
- A final project presentation (organized during the January exam session) - 15 points
It should be noted that, if the student and the teacher agree beforehand via Email, the examination of the second session can be done as an oral exam instead of a written one.
Other information
None
Online resources
Bibliography
Digital Design and Computer Architecture - David Money Harris @ Sarah L. Harris - 2007, Elsevier
Faculty or entity