Public thesis defense Yiyi Yan - ICTEAM
sst |
Advanced Interface Characterization for RF SiGe-engineered Substrates and Al2O3 Gate Dielectric
Thursday July 2nd, 2026 - 4:30pm - Auditorium SUD01 - Place Croix du Sud, 1 - 1348 Louvain-la-Neuve
This thesis investigates advanced interface characterizations of both RF buried SiGe high-resistivity silicon (HR Si) substrates and Metal-Oxide-Semiconductor (MOS) capacitors with various Al2O3 dielectric stacks. Relying primarily on capacitance–voltage (C–V) characterization, the work evaluates different interface trap density (Dit) extraction techniques and addresses admittance-related phenomena that cause extraction inaccuracies. The advanced interface characterizations are applied in two main technological contexts:
Buried SiGe Substrates for RF/mm-Wave Apps: To preserve substrate high resistivity, this thesis introduces a novel passivation scheme using an epitaxial SiGe layer buried beneath the oxide. The higher Dit inherently caused by interfacial Ge–O bonds pins the Fermi level deep in the band gap, reducing free-carrier concentration. Additionally, this buried layer can induce beneficial tensile strain to boost transistor mobility in Ultra-Thin Body and BOX (FDSOI) devices.
Al2O3/SiO2 Dielectric Stacks in MOS Capacitors: This thesis evaluates Al2O3/SiO2 dielectric stacks for advanced CMOS gate-stack applications by comparing different fabrication methods via C–V, G–V, and I–V measurements. Key parameters—including equivalent oxide thickness (EOT), series resistance, fixed oxide charge density (Qf), and interface trap density (Dit)—were reliably extracted. The strong agreement between the two interface trap density extraction methods—the Terman and conductance methods—demonstrates the reliability of this advanced interface characterization.
To evaluate these substrates, Dit, effective resistivity (ρeff), and linearity are defined as key figures of merit. The thesis demonstrates that C–V characteristics differ considerably between standard- and high-resistivity silicon, proving that a simple parallel RC network fails to model high-resistivity substrates at high frequencies. A new de-embedding model for HR Si is developed in the thesis. Finally, RF characterizations of ρeff and linearity are detailed, serving as vital metrics to control substrate loss, coupling, and signal distortion in demanding front-end telecommunication circuitry.
Jury members
Prof. Jean-Pierre Raskin (UCLouvain), Supervisor
Prof. Denis Flandre (UCLouvain), Supervisor
Prof. Laurent Francis (UCLouvain), Chairperson
Prof. Christophe Craeye (UCLouvain)
Dr. Valeria Kilchytska (UCLouvain), Secretary
Prof. Sorin Cristoloveanu, IMEP - INP Grenoble MINATEC, France
Dr. Mostafa Emam, Incize, Belgium