Papier de conférence
Masarweh, E., & Flandre, D. (2025). Mechanical Characterization of Fully Flexible Polyimide Membrane-Substrate Integration. Measuring By Light (MBL2025), Liège, Belgium.
Brandsteert, G., Van Brandt, L., & Flandre, D. (2025). Reliability Analyses of Ultra-Low Voltage Analog Spiking Neurons. 025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES), p. 156-160. https://doi.org/10.23919/MIXDES66264.2025.11092240
Favresse, S., Maistriaux, P., Harpe, P., Flandre, D., & Bol, D. (2025). An Ultra-Low-Power Dual-Channel Analog Front End for Vagus Nerve Sensing with Chopping-Minimized Gain Mismatch. 2025 IEEE Biomedical Circuits and Systems Conference (BioCAS), 121-125. https://doi.org/10.1109/BioCAS67066.2025.00036 (Original work published 2025)
Van Brandt, L., Bidoul, N., Ratier, T., Brandsteert, G., Delvenne, J.-C., Zeng, X., & Flandre, D. (2025). Temperature-Sensitive Spiking Neurons Implemented with Microfabricated Vanadium Dioxide Memristors. IEEE EDS Mini-Colloquium FET100 - Emerging Solutions Toward Sustainable Electronics: From Concept To Implementation, Siania (Roumanie).
Gabbouj, R., Zeidi, N., Flandre, D., & Tounsi, F. (2025). Single- versus Double-layer Spiral Inductor on High-Resistivity Trap-Rich Silicon Substrate. 2025 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 1-6. https://doi.org/10.1109/DTIP66728.2025.11099177 (Original work published 2025)
Ozturk, O., Zeidi, N., Tounsi, F., Flandre, D., & Murat Kaya Yapici. (2025). Modeling and Lumped-Element Extraction of PCB-Based Laterally Coupled Coplanar Transformers. 2025 26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and M. Published. 2025 26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and, Utrecht, Netherlands. https://doi.org/10.1109/EuroSimE65125.2025.11006563 (Original work published 2025)
Van Brandt, L., Brandsteert, G., Bidoul, N., Ratier, T., Zeng, X., Delvenne, J.-C., & Flandre, D. (2025). Excitability of Analog Spiking Neurons. GdR BioComp, Aussois (France).
Nasr, D., Bau, M., Nastro, A., Bertelli, S., Ferrari, M., Said, M. H., Flandre, D., Mansour, M., Tounsi, F., & Ferrari, V. (2025). MEMS Variable Reluctance Sensor Based on a Micromachined Coil. Sensors and Microsystems. AISEM 2025. Lecture Notes in Electrical Engineering, p. 164-169. https://doi.org/10.1007/978-3-032-08271-8_26
Lahaye, L., Raskin, J.-P., & Flandre, D. (2025). Fabrication of Vanadium Dioxide Resistors on Fully-released Polyimide Thin Films for High Strain Studies. Micro and Nano Engineering. Published. Micro and Nano Engineering 2025, Southampton, Angleterre. (Original work published 2025)
Van Brandt, L., Bidoul, N., Ratier, T., Brandsteert, G., Delvenne, J.-C., Zeng, X., & Flandre, D. (2025). Temperature-Sensitive Spiking Neurons Implemented with Microfabricated Vanadium Dioxide Memristors. IEEE EDS Mini-Colloquium FET100 - Emerging Solutions Toward Sustainable Electronics: From Concept To Implementation, Edimbourg (UK).
Zardi, N., Shirin, A., Masmoudi, M., Danlée, Y., Tounsi, F., & Flandre, D. (2025). Cupric Oxide-Coated PCB-based Interdigitated Transducer for Acetone Sensing. 2025 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP). Published. 2025 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), Split, Croatia. https://doi.org/10.1109/DTIP66728.2025.11099216 (Original work published 2025)
Ozturk, O., Tounsi, F., Francis, L., Flandre, D., & Murat Kaya Yapici. (2025). Multiphysics Modeling of a Novel MEMS Accelerometer Based on Electromagnetic Induction. 2025 26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and M. Published. 2025 26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and M, Utrecht, Netherlands. https://doi.org/10.1109/EuroSimE65125.2025.11006620 (Original work published 2025)
Article de journal
Long Chen, Zheyi Lu, Yu Song, Runtong Guo, Hongfu Li, Raskin, J.-P., Flandre, D., Yuan Liu, Lei Liao, & Li, G. (2025). Quantum capacitance impact on low-frequency noise in MoS2 transistors. Physical Review Applied, 23(5), 54012. https://doi.org/10.1103/PhysRevApplied.23.054012 (Original work published 2025)
Scaffidi, R., Jimenez-Arguijo, A., Gong, Y., Brammertz, G., Basak, A., Jehl Li-Kao, Z., Saucedo, E., Flandre, D., & Vermang, B. (2025). Modeling of current-voltage characteristics of high-efficiency kesterite solar cells. Newton, 1(7), 100198. https://doi.org/10.1016/j.newton.2025.100198 (Original work published 2025)
Lahaye, L., Roisin, N., André, N., Flandre, D., & Raskin, J.-P. (2025). Design, Fabrication, Modeling and Characterization of a Polyimide-Based Membrane for High Strain Studies in Microfabricated Devices. IEEE Transactions on Semiconductor Manufacturing, 3, 26-33. https://doi.org/10.1109/TMAT.2025.3557763 (Original work published 2025)
Long Chen, Liting Liu, Hongfu Li, Xingqiang Liu, Yuan Liu, Raskin, J.-P., Flandre, D., & Li, G. (2025). Mechanisms of forward current transport in vertical nanoscale devices: insights and applications. Nano Express, 6(1). https://doi.org/10.1088/2632-959X/ad9853 (Original work published 2025)
Zeidi, N., Gabbouj, R., Raskin, J.-P., Tounsi, F., & Flandre, D. (2025). High-Resistivity Trap-Rich Silicon Substrate Advantages for Large Integrated MIM Capacitors. IEEE Transactions on Electron Devices, 1-7. https://doi.org/10.1109/TED.2025.3622098 (Original work published 2025)
Roisin, N., Lahaye, L., Raskin, J.-P., & Flandre, D. (2025). Electron mobility in silicon under high uniaxial strain. Solid-State Electronics, 227. https://doi.org/10.1016/j.sse.2025.109118 (Original work published 2025)
Gomeniuk Y V, Lytvyn P M, Gomeniuk Y Y, Rudenko T E, Vasin A V, Rusavsky A V, Lysenko V S, Kilchytska, V., Flandre, D., & Nazarov A N. (2025). Charge transport and charge trapping in polycrystalline ZnO thin films doped by methane: local and integrated analysis. Physica Scripta : an international journal for experimental and theoretical physics, 100(2). https://doi.org/10.1088/1402-4896/ada4ea (Original work published 2025)
Gong, Y., Jimenez‐Arguijo, A., Caño, I., Scaffidi, R., Malerba, C., Valentini, M., Payno, D., Navarro‐Güell, A., Segura‐Blanch, O., Flandre, D., Vermang, B., Perez‐Rodriguez, A., Giraldo, S., Placidi, M., Jehl Li‐Kao, Z., & Saucedo, E. (2025). Attaining 15.1% Efficiency in CZTS Solar Cells Under Indoor Conditions Through Sodium and Lithium Co-doping. Solar RRL, 9(4), 2400756. https://doi.org/10.1002/solr.202400756 (Original work published 2025)
Zeidi, N., Tounsi, F., Raskin, J.-P., & Flandre, D. (2025). Vialess non-spiral on-chip stacked transformer on high-resistivity silicon for improved RF power transfer efficiency. Microelectronic Engineering, 302, 112424. https://doi.org/10.1016/j.mee.2025.112424 (Original work published 2026)
Lahaye, L., Roisin, N., André, N., Flandre, D., & Raskin, J.-P. (2025). Design, Fabrication, Modelling and Characterization of a Polyimide-Based Membrane for High Strain Studies in Microfabricated Devices. IEEE Transactions on Materials for Electron Devices, 2, 26-33. https://doi.org/10.1109/TMAT.2025.3557763 (Original work published 2025)
Flandre, D., Brammertz, G., Scaffidi, R., & et al. (2025). Investigation of Recombination Mechanisms in Electronic Devices Using Bias-dependent Admittance Spectroscopy Applied to CIGS Solar Cells. ACS Applied Materials & Interfaces, 17(33), 46998-47008. https://doi.org/10.1021/acsami.5c09671 (Original work published 2025)
Chen, Q., Van Brandt, L., Kilchytska, V., Bestelink, E., Sporea, R. A., & Flandre, D. (2025). Low-frequency noise in polysilicon Source-Gated Thin-Film transistors. Solid-State Electronics, 109099. https://doi.org/10.1016/j.sse.2025.109099 (Original work published 2025)
Flandre, D., Raskin, J.-P., Hong, R., & et al. (2025). Symmetrical Ambipolar Transport in SnO Thin-Film Transistors Enabled by Dopant-Induced Preferential Crystal Orientation toward Complementary Logic. Nano Letters, 25(43), 15698-15704. https://doi.org/10.1021/acs.nanolett.5c04300 (Original work published 2025)
El Khouja, O., Gong, Y., Jimenez-Arguijo, A., Jimenez Guerra, M., Gon Medaille, A., Scaffidi, R., Basak, A., Radu, C., Flandre, D., Vermang, B., Giraldo, S., Placidi, M., Jehl Li-Kao, Z., Catalin Galca, A., & Saucedo, E. (2025). Exploring the Synthesis of Cu2(Zn,Cd)SnS4 at High Temperatures as a Route for High-Efficiency Solar Cells. Exploring the Synthesis of Cu2(Zn,Cd)SnS4 at High Temperatures as a Route for High-Efficiency Solar Cells, 1(1), 1-16. https://doi.org/10.1002/pip.3899 (Original work published 2025)
Van Brandt, L., Bonnin, M., Banaszeski da Sila, M., Bolcato, P., Wirth, G. I., & Flandre, D. (2025). Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 72(34), 989-1002. https://doi.org/10.1109/TCSI.2024.3525387 (Original work published 2025)
Zeng, X., André, N., Masarweh, E., Bonfanti, O., & Flandre, D. (2025). Electromechanical Measurements and Modeling of a High-Performance Small-Area Ultra-Thin SOI MEMS Piezoresistive Pressure Sensor. IEEE Transactions on Instrumentation and Measurement, 74(7507509), 1-9. https://doi.org/10.1109/TIM.2025.3566836 (Original work published 2025)
Zeidi, N., Tounsi, F., Raskin, J.-P., & Flandre, D. (2025). Trap-rich high-resistivity silicon for improved on-chip monolithic transformers characteristics. Solid-State Electronics, 230. https://doi.org/10.1016/j.sse.2025.109261 (Original work published 2025)
Song Yu, Runtong Guo, Ruohao Hong, Rui He, Xuming Zou, Benjamin Iñiguez, Flandre, D., Lei Liao, & Li, G. (2025). Improving electrical performance and fringe effect in p-type SnOx thin film transistors via Ta incorporation. Journal of Semiconductors, 46(9). https://doi.org/10.1088/1674-4926/25010031 (Original work published 2025)
Kotagama Virendra, Renz Arne Benjamin, Melnyk Kyrylo, Kilchytska, V., Flandre, D., & Shah V.A. (2025). Total Ionising Dose effects in commercial 4H-SiC MOSFETs. IEEE Transactions on Nuclear Science, 1. https://doi.org/10.1109/TNS.2025.3645913 (Original work published 2025)
Tyagulski, I. P., Gudymenko, O. Yo., Rusavsky, A. V., Tiagulskyi, S. I., Flandre, D., & et al. (2025). Flash lamp annealing of Cu(In1–xGax)SSe films deposited on polyimide substrate: Crystalline structure and chemical composition. Fizika Napivprovidnikiv Kvantova ta Optoelektronika, 28(2), 232-238. https://doi.org/10.15407/spqeo28.02.232 (Original work published 2025)
Klauner, T., Roisin, N., Bonfanti, O., Sabri Alirezaei, I., André, N., & Flandre, D. (2025). Radiation Degradation and Mitigation of an Ultrathin SOI SPAD Using a Perimeter Gate. IEEE Transactions on Electron Devices, 72(4), 1844-1850. https://doi.org/10.1109/TED.2025.3543789 (Original work published 2025)
Papier de conférence
Colla, M.-S., Roisin, N., Flandre, D., Raskin, J.-P., Pardoen, T., & et al. (2024). Strain engineering of thin semiconductor films investigated using the residual-stress-actuated on-chip testing method. 19th European Mechanics of Materials Conference - EMMC19, Madrid.
Van Brandt, L., Flandre, D., & Delvenne, J.-C. (2024). Stochastic Nonlinear Dynamical Modelling of SRAM Bitcells in Retention Mode. IEEE Xplore. Published. 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India. https://doi.org/10.1109/edtm58488.2024.10512067
Colla, M.-S., Naceri, S. E., Roisin, N., Baral, P., Coulombier, M., Idrissi, H., Flandre, D., Raskin, J.-P., & Pardoen, T. (2024). New developments of the residual stress actuated on-chip testing method. 2nd MecaNano General Meeting, Vienna.
Favresse, S., Bol, D., & Flandre, D. (2024). A 1.88-NEF 3-kHz Current-Reuse Common-Gate Amplifier Featuring Resistorless High-Pass Filtering. Proceedings of the 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS). Published. IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nancy, France. https://doi.org/10.1109/ICECS61496.2024.10848910 (Original work published 2024)
Van Brandt, L., Delvenne, J.-C., & Flandre, D. (2024). Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells. IEEE Xplore. Published. 2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS), Punta del Este, Uruguay. https://doi.org/10.1109/lascas60203.2024.10506179
Chouaibi, S., Said Hadj, M., Imburgia, A., Romano, P., Kaziz, S., Ala, G., Ben Ayed, M., Flandre, D., & Tounsi, F. (2024). Inductive Loop Operation Versus Loop Antenna for Partial Discharge Detection. 2024 IEEE 5th International Conference on Dielectrics (ICD), 1-4. https://doi.org/10.1109/ICD59037.2024.10613039 (Original work published 2024)
Lahaye, L., Roisin, N., Raskin, J.-P., & Flandre, D. (2024). Accurate estimation of Young’s modulus of VO2 thin film integrated on polyimide for high strain studies. Measuring By Light 2025, Delft, Pays-Bas.
Bidoul Noemie, Pauline Raux, Van Aerschot, T., Alex Pip, Renaux, C., Faniel, S., Flandre, D., & Raskin, J.-P. (2024). Process-Based Life Cycle Assessment of a Vanadium Dioxide Spiking Neuron. 2024 Electronics Goes Green 2024+ (EGG). Published. 2024 Electronics Goes Green 2024+ (EGG), Berlin, Germany. https://doi.org/10.23919/EGG62010.2024.10631188
Article de journal
Sinda Kaziz, Pietro Romano, Giovanni Artale, Giuseppe Rizzo, Fabio Viola, Guido Ala, Flandre, D., Tounsi, F., Antonino Imburgia, & et al. (2024). Printed-Board Inductive Loop Topologies Performance for Partial Discharges Detection. IEEE Transactions on Industry Applications, 60(4). https://doi.org/10.1109/TIA.2024.3384134 (Original work published 2024)
Scaffidi, R., Gong, Y., Jimenez-Arguijo, A., Medaille, A. G., Suresh, S., Brammertz, G., Giraldo, S., Puigdollers, J., Flandre, D., Vermang, B., & Saucedo, E. (2024). Tuning the bandgap without compromising efficiency: Ambient solution processing of Ge-alloyed (Ag,Cu)2Zn(Sn,Ge)(S,Se)4 kesterite thin-film solar cells. Materials Today Energy, 46(1), 101715. https://doi.org/10.1016/j.mtener.2024.101715 (Original work published 2024)
Gong, Y., Jimenez‐Arguijo, A., Medaille, A. G., Moser, S., Basak, A., Scaffidi, R., Carron, R., Flandre, D., Vermang, B., Giraldo, S., Xin, H., Perez‐Rodriguez, A., & Saucedo, E. (2024). Li‐Doping and Ag‐Alloying Interplay Shows the Pathway for Kesterite Solar Cells with Efficiency Over 14%. Advanced Functional Materials, 34(42), 2404669. https://doi.org/10.1002/adfm.202404669 (Original work published 2024)
Kotagama, V., Renz, A. B., Kilchytska, V., Flandre, D., Qi, Y., Shah, V. A., Antoniou, M., & Gammon, P. M. (2024). Investigations into the Impact of Deposition or Growth Techniques on the Field Oxide TID Response for 4H-SiC Space Applications. Solid State Phenomena, 362, 83-88. https://doi.org/10.4028/p-4px5zX (Original work published 2024)
Zeng, X., Zhukova, M., Faniel, S., Li, G., & Flandre, D. (2024). Properties and Aging of Bottom-Contact CuO/Au Transmission Line Model (TLM) Structures. IEEE Transactions on Electron Devices, 6254-6260. (Original work published 2024)
Roisin, N., Brunin, G., Rignanese, G.-M., Flandre, D., Raskin, J.-P., & Poncé, S. (2024). Phonon-limited mobility for electrons and holes in highly-strained silicon. npj Computational Materials, 10(1), 242. https://doi.org/10.1038/s41524-024-01425-0 (Original work published 2024)
Chen, Q., Zeng, X., & Flandre, D. (2024). Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors. Solid-State Electronics, 214, 108878. https://doi.org/10.1016/j.sse.2024.108878 (Original work published 2024)
Parion, J., Scaffidi, R., Duerinckx, F., Sivaramakrishnan, H., Flandre, D., Poortmans, J., & Vermang, B. (2024). Comparative study of the interface passivation properties of LiF & Al2O3 using silicon MIS capacitor. Applied Physics Letters, 124(14), 142901. https://doi.org/10.10363/5.0203484 (Original work published 2024)
Bidoul Noemie, Roisin, N., & Flandre, D. (2024). Tuning the Intrinsic Stochasticity of Resistive Switching in VO2 Microresistors. Nano Letters : a journal dedicated to nanoscience and nanotechnology, 24(21), 6201-6209. https://doi.org/10.1021/acs.nanolett.4c00184 (Original work published 2024)
Favresse, S., Bol, D., & Flandre, D. (2024). A Combined Analytical and Simulation-Based Methodology for Quantifying the Noise-Power-Area Trade-Offs in Biomedical Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers, 71(12), 6177-6189. https://doi.org/10.1109/TCSI.2024.3414649 (Original work published 2024)
Hong, R., He, P., Zhang, S., Hong, X., Tian, Q., Liu, C., Bu, T., Su, W., Li, G., Flandre, D., & et al. (2024). Compositional Engineering of Cu-Doped SnO Film for Complementary Metal Oxide Semiconductor Technology. Nano Letters : a journal dedicated to nanoscience and nanotechnology, 24(4), 1176-1183. https://doi.org/10.1021/acs.nanolett3c03953 (Original work published 2024)
Masarweh, E., Arseenko, M., Guaino, P., & Flandre, D. (2024). Membrane-based mechanical characterization of screen-printed inks: Deflection analysis of ink layers on polyimide membranes. Applied Research. Published. https://doi.org/10.1002/appl.202300113 SECTIONS (Original work published 2024)
Article de journal
Xie, Z., Li, G., Xia, S., Liu, C., Zhang, S., Flandre, D., & et al. (2023). Ultimate Limit in Optoelectronic Performances of Monolayer WSe2 Sloping-Channel Transistors. Nano Letters : a journal dedicated to nanoscience and nanotechnology, 23, 6664-6672. https://doi.org/10.1021/acs.nanolett.3c01866 (Original work published 2023)
Afzalian, A., & Flandre, D. (2023). Ultra-Scaled Si Nanowire Biosensors for Single DNA Molecule Detection. Sensors, 23(12), 5405. https://doi.org/10.3390/s23125405 (Original work published 2023)
Roisin, N., Colla, M.-S., Raskin, J.-P., & Flandre, D. (2023). Raman Strain-Shift Measurements and Prediction from First-Principles in Highly-Strained Silicon. Journal of Materials Science: Materials in Electronics, 34, 373. https://doi.org/10.1007/s10854-022-09769-3 (Original work published 2023)
Scaffidi, R., Brammertz, G., Wang, Y., Zaman, A. U., Sasikumar, K., de Wild, J., Flandre, D., & Vermang, B. (2023). A study of bandgap-graded CZTGSe kesterite thin films for solar cell applications. Energy Advances, 2(10), 1626. https://doi.org/10.1039/d3ya00359k (Original work published 2023)
Kaziz, S., Hadj Said, M., Imburgia, A., Maamer, B., Flandre, D., Romano, P., & Tounsi, F. (2023). Radiometric Partial Discharge Detection: A Review. energies, 16(4), 1978. https://doi.org/10.3390/en16041978 (Original work published 2023)
Xu, P., Flandre, D., & Bol, D. (2023). Analysis and Design of RF Energy-Harvesting Systems with Impedance-Aware Rectifier Sizing. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, 70(2), 367-365. https://doi.org/10.1109/TCSII.2022.3171470 (Original work published 2023)
Vanbrabant, M., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2023). Impact of thermal coupling effects on the digital and analog figures of merit of UTBB SOI MOSFET pairs. Solid-State Electronics, 2023, 108623. https://doi.org/10.1016/j.sse.2023.108623 (Original work published 2023)
Lefebvre, M., Flandre, D., & Bol, D. (2023). A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. IEEE Journal of Solid State Circuits, 58(8), 2239-2251. https://doi.org/10.1109/jssc.2023.3240209 (Original work published 2023)
Scaffidi, R., Birant, G., Brammertz, G., de Wild, J., Flandre, D., & Vermang, B. (2023). Ge-alloyed kesterite thin-film solar cells: previous investigations and current status – a comprehensive review. Journal of Materials Chemistry A, 11(25), 13174-13194. https://doi.org/10.1039/d3ta01218b (Original work published 2023)
Yan, Y., Kilchytska, V., Flandre, D., & Raskin, J.-P. (2023). Analysis of trap distribution and NBTI degradation in Al2O3/SiO2 dielectric stack. Solid-State Electronics, 207(207). https://doi.org/10.1016/j.sse.2023.108675 (Original work published 2023)
Van Brandt, L., Silveira, F., Delvenne, J.-C., & Flandre, D. (2023). On noise-induced transient bit flips in subthreshold SRAM. Solid-State Electronics, 208, 108715. https://doi.org/10.1016/j.sse.2023.108715 (Original work published 2023)
Roisin, N., Colla, M.-S., Scaffidi, R., Pardoen, T., Flandre, D., & Raskin, J.-P. (2023). Band gap reduction in highly-strained silicon beams predicted by first-principles theory and validated using photoluminescence spectroscopy. Optical Materials, 144(114347), 1-10. https://doi.org/10.1016/j.optmat.2023.114347 (Original work published 2023)
Qaderi, F., Rosca, T., Burla, M., Leuthold, J., Flandre, D., & Ionescu, A. M. (2023). Millimeter-wave to near-terahertz sensors based on reversible insulator-to-metal transition in VO2. Communications Materials, 34. https://doi.org/10.1038/s43246-023-00350-x (Original work published 2023)
Zhou, Y., Song, Y., Hong, R., Liu, X., Zou, X., Iniguez, B., Flandre, D., Li, G., & Liao, L. (2023). Electrical Evolution of p-Type SnO Film and Transistor Deposited by RF Magnetron Sputtering. IEEE Transactions on Electron Devices, 70(6), 3100-3105. (Original work published 2023)
Puyol Troisi, R., Walewyns, T., Francis, L., & Flandre, D. (2023). Design of Ultra-Low-Power Sensor Readout Circuits Through Adaptive Biasing for Gas Monitoring With Chemiresistive Sensors. IEEE Sensors Journal, 23(22), 27468-27477. https://doi.org/10.1109/JSEN.2023.3322393 (Original work published 2023)
Papier de conférence
Bidoul, N., Rosca, T., Ionescu, A. M., & Flandre, D. (2023). Static and Dynamic Stochastic Analysis of a Temperature-Sensitive VO2 Spiking Neuron. 53rd European Solid-State Device Research Conference (ESSDERC). Published. 53rd European Solid-State Device Research Conference (ESSDERC), Lisbon, Portugal. https://doi.org/10.1109/ESSDERC59256.2023.10268509
Bidoul, N., & Flandre, D. (2023). Bio-inspired Encoding of Heat Using VO2 Neuron Operated in Stochastic Bursting Regime. Proceedings of Neuronics Conference (Neuronics), València, Spain.
Klauner, T., Alirezaei, I. S., Roisin, N., André, N., & Flandre, D. (2023). SPICE Model of SPAD Transient Intrinsic Response Validated using Mixed-Mode TCAD Simulations. ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC), Lisbon, Portugal.
Van Brandt, L., Silveira, F., Delvenne, J.-C., & Flandre, D. (2023). On Noise-Induced Transient Bit Flips in Subthreshold SRAM. 9th EUROSOI-ULIS, Tarragona, Spain.
Van Brandt, L., Vercauteren, R., Haya Enriquez, D., André, N., Kilchytska, V., Flandre, D., & Delvenne, J.-C. (2023). Variance and Skewness of Current Fluctuations Experimentally Evidenced in Single-Photon Avalanche Diodes. 2023 International Conference on Noise and Fluctuations (ICNF). Published. 2023 International Conference on Noise and Fluctuations (ICNF), Grenoble, France. https://doi.org/10.1109/ICNF57520.2023.10472747
Roisin, N., Colla, M.-S., Scaffidi, R., Pardoen, T., Flandre, D., & Raskin, J.-P. (2023). Band gap narrowing in highly-strained silicon beams observed using photoluminescence spectroscopy. BePOM 2023, Bruxelles.
Parion, J., Scaffidi, R., Flandre, D., Brammertz, G., & Vermang, B. (2023). Low-temperature admittance spectroscopy for defect characterization in Cu(In,Ga)(S,Se)2 thin-film solar cells. IEEE EUROCON 2023 - 20th International Conference on Smart Technologies. Published. IEEE EUROCON 2023 - 20th International Conference on Smart Technologies, Torino, Italy. https://doi.org/10.1109/EUROCON56442.2023.10199008
Chouaibi, S., Said, M. H., Nasr, D., Ayed, M. B., Flandre, D., & Tounsi, F. (2023). Mutual Inductance Evaluation Between Two Parallel Conductors on a PCB. 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS). Published. 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkey. https://doi.org/10.1109/ICECS58634.2023.10382803
Masarweh, E., Arseenko, M., Guaino, P., & Flandre, D. (2023). Membrane-based mechanical characterization of screenprinted ink films. International Symposium on Flexible Organic Electronics (ISFOE23), Thessalonique, Grèce.
Zeidi, N., André, N., Tounsi, F., & Flandre, D. (2023). Improving Dielectric Constant and Residual Stress in Metal-Insulator-Metal Capacitors Using Different Stacked Thick Dielectric Materials. 2023 International Semiconductor Conference (CAS). Published. 2023 International Semiconductor Conference (CAS), Sinaia, Romania. https://doi.org/10.1109/CAS59036.2023.10303695
Roisin, N., Raskin, J.-P., & Flandre, D. (2023). Near-IR response of highly-strained Si photodetector linking first principles and TCAD. ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC), 1(1), 1-9. https://doi.org/10.1109/ESSDERC59256.2023.10268568 (Original work published 2023)
Van Brandt, L., Silveira, F., Delvenne, J.-C., Bol, D., & Flandre, D. (2023). Variability and Intrinsic Noise Effects in ULV CMOS SRAM Demystified. IEEE Latin American Electron Devices Conference 2023, Puebla, Mexico.
Zeidi, N., Rack, M., André, N., Tounsi, F., Raskin, J.-P., & Flandre, D. (2023). Effect of Silicon Substrate Resistivity on Large- Area High-Voltage Spiral Inductor Performance. 2023 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS. Published. 2023 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS, Valetta, Malta. https://doi.org/10.1109/DTIP58682.2023.10267935
Van Brandt, L., & Flandre, D. (2023). Estimation analytique des taux de défaillance dans les SRAM sous seuil en régime de rétention de données. FETCH 2023, Lavey-les-Bains (Vaud, Suisse).
Bidoul, N., Huet, B., Ureña Begara, F., Raskin, J.-P., & Flandre, D. (2023). Tuning the stochasticity of VO2 neurons firing-threshold through grain size engineering. Proceedings of Neuromorphic Materials, Devices, Circuits and Systems, p. 050. https://doi.org/10.29363/nanoge.neumatdecas.2023.050
Melinte, S., Yunda Sangoluisa, J. A., Torres Llerena, G., Flandre, D., & et al. (2023). Multimodal machine learning in chronic wound management: A bright future for biomaterials and soft materials. EMRS Spring Meeting, Strasbourg.
Francis, L., Roisin, N., Colla, M.-S., Flandre, D., & Raskin, J.-P. (2023). Improving the determination of strain in the deformed Silicon measured by Raman spectroscopy. International Meeting on Optical Measurement Techniques and Industrial Applications. Published. International Meeting on Optical Measurement Techniques and Industrial Applications, Delft (Netherlands).
Chen, Q., & Flandre, D. (2023). TCAD Simulation Study on P-type Source-gated CuO TFTs. Symposium on Schottky Barrier MOS 2023 “The Schottky barrier transistor in emerging electronic devices”, Paris, France.
Brevet
Roisin, N., Flandre, D., André, N., & Delhaye, T. (2023). Strain sensor.
Xu, P., Bol, D., & Flandre, D. (2023). Energy harvesting system.
Papier de conférence
Roth, F., Bidoul, N., Rosca, T., D¨orpinghaus, M., Flandre, D., Ionescu, A. M., & Fettweis, G. (2022). Spike-Based Sensing and Communication for Highly Energy-Efficient Sensor Edge Nodes. 2022 2nd IEEE International Symposium on Joint Communications & Sensing (JC&S), Seefeld (Austria).
Roisin, N., Colla, M.-S., Flandre, D., Raskin, J.-P., & et al. (2022). Raman Shift Prediction from First Principles in Highly-Strained Silicon. ICOOPMA 2022, Gent.
Lefebvre, M., Flandre, D., & Bol, D. (2022). A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI. Proceedings of the ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 469-472. https://doi.org/10.1109/ESSCIRC55480.2022.9911369 (Original work published 2022)
Vanbrabant, M., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2022). Experimental study of thermal coupling effects in FD-SOI MOSFET. The 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon - EuroSOI-ULIS′2022. Published. The 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon - EuroSOI-ULIS′2022, Udine, Italy.
Kaziz, S., Imburgia, A., Flandre, D., Rizzo, G., Romano, P., Viola, F., Ala, G., & Tounsi, F. (2022). Performances of a PCB-based Loop Antenna Inductive Sensor for Partial Discharges Detection. Proceedings of the 2022 IEEE 4th International Conference on Dielectrics (ICD 2022), 9-12. https://doi.org/10.1109/ICD53806.2022.9863503
Yan, Y., Reckinger, N., Kilchytska, V., Flandre, D., Tang, X., Malik, M. W., Hackens, B., & Raskin, J.-P. (2022). Hexagonal Boron Nitride Memristor based on a nanogap self-formed by silicidation. Mini Colloquia (MQ) on “Memristive Devices”, The 6th Symposium on Schottky Barrier MOS Devices (SSBMOS), Giessen, Germany.
Yan, Y., Kilchytska, V., Faniel, S., Flandre, D., & Raskin, J.-P. (2022). Investigation and optimization of traps properties in Al2O3/SiO2 dielectric stacks. The 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon - EuroSOI-ULIS′2022. Published. The 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon - EuroSOI-ULIS′2022, Udine, Italy.
Imburgia, A., Kaziz, S., Romano, P., Flandre, D., Artale, G., Rizzo, v., Viola, F., Tounsi, F., & Ala, G. (2022). Investigation of PCB-based Inductive Sensors Orientation for Corona Partial Discharge Detection. proceedings of the 2022 IEEE 21st Mediterranean Electrotechnical Conference, 559-563. https://doi.org/10.1109/MELECON53508.2022.9843026
Roisin, N. (2022). Optical performances prediction of highly strained silicon photodetector. 7th edition of the silicon photonics Summer School, C2N Paris-Saclay, France.
Article de journal
Kaziz, S., Romano, P., Imburgia, A., Ala, G., Sghaier, H., Flandre, D., & Tounsi, F. (2022). PCB-Based Planar Inductive Loops for Partial Discharges Detection in Power Cables. Sensors, 23(1), 290. https://doi.org/10.3390/s23010290 (Original work published 2022)
Yan, Y., Kilchytska, V., Flandre, D., & Raskin, J.-P. (2022). Investigation and optimization of traps properties in Al2O3/SiO2 dielectric stacks using conductance method. Solid-State Electronics, 194, 4. https://doi.org/10.1016/j.sse.2022.108347 (Original work published 2022)
Vanbrabant, M., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2022). Experimental study of thermal coupling effects in FD-SOI MOSFET. Solid-State Electronics, 194(108362), 4. https://doi.org/10.1016/j.sse.2022.108362 (Original work published 2022)
D. Martinez-Perez, A., Aznar, F., Flandre, D., & Celma, S. (2022). Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs. I E E E Access, 10, 29482-29492. https://doi.org/10.1109/ACCESS.2022.3158356 (Original work published 2022)
Roisin, N., Delhaye, T., André, N., Raskin, J.-P., & Flandre, D. (2022). Low-Power Silicon Strain Sensor Based on CMOS Current Reference Topology. Sensors and Actuators A: Physical : an international journal devoted to research and development of physical and chemical transducers, 339(113491), 1-11. https://doi.org/10.1016/j.sna.2022.113491 (Original work published 2022)
Yan, Y., Kilchytska, V., Bin, W., Faniel, S., Zeng, Y., Raskin, J.-P., & Flandre, D. (2022). Characterization of thin Al2O3/SiO2 dielectric stack for CMOS transistors. Microelectronic Engineering, 254(111708), 7. https://doi.org/10.1016/j.mee.2022.111708 (Original work published 2022)
Oliveira, K., P. Teixeira, J., Chen, W.-C., Lontchi Jioleo, J., J. N. Oliveira, A., Çaha, I., Deepak Francis, L., Flandre, D., Edoff, M., A. Fernandes, P., & M. P. Salomé, P. (2022). SiOx Patterned Based Substrates Implemented in Cu(In,Ga)Se2 Ultrathin Solar Cells: Optimum Thickness. I E E E Journal of Photovoltaics, 8. (Original work published 2022)
Zeng, X., Lontchi Jioleo, J., Zhukova, M., Bolt, P., Smor, M., Fourdrinier, L., Li, G., & Flandre, D. (2022). High-performance dual-mode ultra-thin broadband CdS/CIGS heterojunction photodetector on steel. Optics Express, 30(8), 13875-13889. https://doi.org/10.1364/OE.456352 (Original work published 2022)
Schramme, M., Van Brandt, L., Flandre, D., & Bol, D. (2022). Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, 69(5), 1883-1895. https://doi.org/10.1109/TCSI.2022.3144527 (Original work published 2022)
Tounsi, F., Hadj Said, M., Hauwaert, M., Kaziz, S., Francis, L., Raskin, J.-P., & Flandre, D. (2022). Variation Range of Different Inductor Topologies with Shields for RF and Inductive Sensing Applications. Sensors, 22(9), 15. https://doi.org/10.3390/s22093514 (Original work published 2022)
Zeng, X., Zhukova, M., Faniel, S., Li, G., & Flandre, D. (2022). Room-temperature DC-sputtered p-type CuO accumulation-mode thin-film transistors gated by HfO2. Applied Physics Letters, 11. https://doi.org/10.1063/5.0098757 (Original work published 2022)
Van Brandt, L., Saeidi, R., Bol, D., & Flandre, D. (2022). Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, 69(7), 2767-2780. https://doi.org/10.1109/TCSI.2022.3164680 (Original work published 2022)
He, P., Ding, C., Li, G., Hu, W., Ma, C., Flandre, D., Iñíguez, B., Liao, L., Lan, L., & Liu, X. (2022). Enhanced Stability and Mobility of Solution-Processed Oxide Thin-Film Transistors with Bilayer Terbium-incorporated Indium Oxide Channel. Applied Physics Letters, 121(19), 21. (Original work published 2022)
Puyol Troisi, R., Pétré, S., Danlée, Y., Walewyns, T., Francis, L., & Flandre, D. (2022). An Ultra-Low-Power Read-Out Circuit for Interfacing Novel Gas Sensors Matrices. IEEE Sensors Journal, 22(10), 9521-9533. https://doi.org/10.1109/JSEN.2022.3165755 (Original work published 2022)
Amor, S., Kilchytska, V., Tounsi, F., André, N., Machhout, M., Francis, L., & Flandre, D. (2022). Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET with in-situ thermal annealing. Solid-State Electronics, Journal pre proof, 20. https://doi.org/10.1016/j.sse.2022.108300 (Original work published 2022)
Article de journal
Xu, P., Flandre, D., & Bol, D. (2021). A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform. IEEE Journal of Solid State Circuits, 56(6), 1816-1826. https://doi.org/10.1109/jssc.2021.3061196 (Original work published 2021)
Schwarz, M., Kloes, A., & Flandre, D. (2021). Temperature-dependent performance of Schottky-Barrier FET ultra-low-power diode. Solid-State Electronics, 184(108124), 8. https://doi.org/10.1016/j.sse.2021.108124 (Original work published 2021)
Scaffidi, R., Buldu, D. G., Brammertz, G., Kohl, T., Birant, G., Meuris, M., Poortmans, J., Flandre, D., & Vermang, b. (2021). Comparative study of Al2O3 and HfO2 for surface passivation of Cu(In,Ga)Se2 thin-films: An innovative Al2O3/HfO2 multi-stack design. Physica Status Solidi A. Published. https://doi.org/10.1002/pssa.202100073 (Original work published 2021)
Wang, B., Malik, M. W., Yan, Y., Kilchytska, V., Zeng, Y., Flandre, D., & Raskin, J.-P. (2021). A Physical Model of Contact Resistance in Ti-Contacted Graphene-Based Field Effect Transistors. IEEE Transactions on Electron Devices, 68(2), 892-898. https://doi.org/10.1109/TED.2020.3046166 (Original work published 2021)
GALEMBECK, E. H. S., Renaux, C., SWART, J. W., Flandre, D., & GIMENEZ, S. P. (2021). The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures. I E E E Journal of the Electron Devices Society, 9, 415-423. https://doi.org/10.1109/JEDS.2021.3071399 (Original work published 2021)
Saoutieff, E., Polichetti, T., Jouanet, L., Faucon, A., Vidal, A., Pereira, A., Boisseau, S., Ernst, T., Miglietta, M. L., Alfano, B., Massera, E., De Vito, S., Bui, D. H. N., Benech, P., Vuong, T.-P., Moldovan, C., Danlée, Y., Walewyns, T., Pétré, S., et al. (2021). A Wearable Low-Power Sensing Platform for Environmental and Health Monitoring: The Convergence Project. Sensors, 21(5), 21. https://doi.org/10.3390/s21051802 (Original work published 2021)
Delhaye, T., André, N., Francis, L., & Flandre, D. (2021). New Universal Figure of Merit for Embedded Si Piezoresistive Pressure Sensors. IEEE SENSORS JOURNAL, 21(1), 213-221. https://doi.org/10.1109/JSEN.2020.3013017 (Original work published 2021)
Chen, Q., Li, G., André, N., Liu, X., Xia, Z., Flandre, D., & Liao, L. (2021). Origin of Low-Temperature Negative Transconductance in Multilayer MoS2 Transistors. Applied Physics Letters, 10. https://doi.org/10.1063/5.0058545 (Original work published 2021)
Sabri Alirezaei, I., André, N., Amor, S., Gérard, P., & Flandre, D. (2021). An Ultra-Thin Ultraviolet Enhanced Backside- Illuminated Single-Photon Avalanche Diode with 650nm-Thin Silicon Body Based on SOI Technology. IEEE Journal of Selected Topics in Quantum Electronics, 11. https://doi.org/10.1109/JSTQE.2021.3129274 (Original work published 2021)
M. V. Cunha, J., Oliveira, K., Lontchi Jioleo, J., S. Lopes, T., A. Curado, M., R. S. Barbosa, J., Vinhais, C., Chen, W.-C., Borme, J., Fonseca, H., Gaspar, J., Flandre, D., Edoff, M., G. Silva, A., P. Teixeira, J., A. Fernandes, P., & M. P. Salomé, P. (2021). High-Performance and Industrially Viable Nanostructured SiOx Layers for Interface Passivation in Thin Film Solar Cells. Solar RRL, 2021(2000534), 13. https://doi.org/10.1002/solr.202000534 (Original work published 2021)
Amor, S., Kilchytska, V., Flandre, D., & Galy, P. (2021). Trap Recovery by in-Situ Annealing in Fully-Depleted MOSFET With Active Silicide Resistor. IEEE Electron Device Letters, 42(7), 1085-1088. https://doi.org/10.1109/LED.2021.3079244 (Original work published 2021)
Wei, P., Sabri Alirezaei, I., André, N., Zeng, X., Bouterfa, M., Wang, B., Zeng, Y., & Flandre, D. (2021). The Shift of Breakdown Voltage for Silicon Membrane Strip Detectors Resulting from Surface Avalanche. Journal of Applied Physics, 129(21), 214501-214501. https://doi.org/10.1063/5.0049490 (Original work published 2021)
Li, G., Fan, Z., André, N., Xu, Y., Xia, Y., Iniguez, B., Liao, L., & Flandre, D. (2021). Non-Linear Output-Conductance Function for Robust Analysis of Two-Dimensional Transistors. IEEE Electron Device Letters, 42(1), 94-97. https://doi.org/10.1109/LED.2020.3042212 (Original work published 2021)
M. V. Cunha, J., Barreiros, M. A., Curado, M. A., Lopes, T. S., Oliveira, K., Oliveira, A. J. N., Barbosa, J. R. S., Vilanova, A., Brites, M. J., Mascarenhas, J., Flandre, D., Silva, A. G., Fernandes, P. A., & Salomé, P. M. P. (2021). Perovskite Metal–Oxide–Semiconductor Structures for Interface Characterization. Advanced Materials Interfaces, 1-12. https://doi.org/10.1002/admi.202101004 (Original work published 2021)
Lontchi Jioleo, J., Doghmen, H., Krumpmann, A., Snyders, R., & Flandre, D. (2021). Depletion effects in moderately doped TiO2 layers from C–V characteristics of MIS structures on Si. Applied Physics Express, 14(5). https://doi.org/10.35848/1882-0786/abfb61 (Original work published 2021)
Roisin, N., Brunin, G., Rignanese, G.-M., Flandre, D., & Raskin, J.-P. (2021). Indirect light absorption model for highly strained silicon infrared sensors. Journal of Applied Physics, 30(5), 30. https://doi.org/10.1063/5.0057350 (Original work published 2021)
Kilchytska, V., Makovejev, S., Esfeh, B. K., Nyssens, L., Halder, A., Raskin, J.-P., & Flandre, D. (2021). Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications. I E E E Journal of the Electron Devices Society, 9, 500-510. https://doi.org/10.1109/JEDS.2021.3057798 (Original work published 2021)
Zeng, X., Lontchi Jioleo, J., Zhukova, M., Fourdrinier, L., Qadir, I., Ren, Y., Niemi, E., Li, G., & Flandre, D. (2021). High-responsivity broadband photodetection of an ultra-thin In2S3/CIGS heterojunction on steel. Optics Letters, 46(10), 2288-2291. https://doi.org/10.1364/OL.423999 (Original work published 2021)
Morelle, A., Vandermolen, E., Kilchytska, V., Raskin, J.-P., & Flandre, D. (2021). Improved Split CV Mobility Extraction in 28 nm Fully Depleted Silicon on Insulator Transistors. IEEE Electron Device Letters, 42(5), 661-664. https://doi.org/10.1109/LED.2021.3065002 (Original work published 2021)
Bol, D., Schramme, M., Moreau, L., Xu, P., Dekimpe, R., Saeidi, R., Haine, T., Frenkel, C., & Flandre, D. (2021). SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE Journal of Solid State Circuits, 56(7), 2256-2269. https://doi.org/10.1109/JSSC.2021.3056219 (Original work published 2021)
Papier de conférence
Oliveira, K., Chen, W.-C., Lontchi Jioleo, J., Oliveira, A. J. N., Teixeira, J. P., Flandre, D., Edoff, M., Fernandes, P. A., & Salomé, P. M. P. (2021). SiOx patterned based substrates implemented in Cu(In,Ga)Se2 ultrathin solar cells: optimum thickness. 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC 2021), virtual conference.
Kilchytska, V., Makovejev, S., Esfeh, B. K., Nyssens, L., Halder, A., Raskin, J.-P., & Flandre, D. (2021). Advanced MOSFETs Electrical Characterization for Further Analog and RF applications. SBMicro, virtual conference.
Delhaye, T. P., Le Brun, G., Flandre, D., & Raskin, J.-P. (2021). Bottom-Up Life-Cycle Assessment of MEMS Piezoresistive Pressure Sensors. Proceedings, p. 1-6. https://doi.org/10.1109/dtip54218.2021.9568683
Zeng, X., Zhukova, M., Faniel, S., Proost, J., & Flandre, D. (2021). Material, optical and electrical characterization of DC sputtered CuO by tuning oxygen concentration. Proceedings of the EMRS-Spring meeting 2021. EMRS-Spring meeting 2021, Virtual meeting.
Delhaye, T., Le Brun, G., Flandre, D., & Raskin, J.-P. (2021). Bottom-Up Life-Cycle Assessment of MEMS Piezoresistive Pressure Sensors. Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, Virtual event.
Li, G., He, J., Flandre, D., & Liao, L. (2021). Defect Engineering in n‐Type Oxide Semiconductor TFTs. International Conference on Display Technology 2021 (ICDT 2021), Beijing (China).
Yan, Y., Flandre, D., Kilchytska, V., Faniel, S., Tang, X., & Raskin, J.-P. (2021). Determination of Carrier Lifetime in Silicon Using an Ultra-thin Al2O3/SiO2 Dielectric Stack. Proceedings of the 2021 IEEE Latin America Electron Devices Conference (LAEDC). 2021 IEEE Latin America Electron Devices Conference (LAEDC), Virtual conference.
Stoukatch, S., André, N., Dupont, F., Redouté, J.-M., & Flandre, D. (2021). Ultra-Thinned Individual SOI Die ACF FC Bonded on Rigid and Flex PCB. Proceedings, p. 1-5. https://doi.org/10.23919/EMPC53418.2021.9584947
Delhaye, T., Roisin, N., André, N., Francis, L., & Flandre, D. (2021). Improving MOSFET Piezoresistive Strain Gauges Limit of Detection Using Lock-In Principle. Proceedings of the IEEE Sensors 2021. IEEE Sensors 2021, virtual conference.
Amor, S., Kilchytska, V., Tounsi, F., André, N., Francis, L., & Flandre, D. (2021). In-situ recovery of on-membrane PD-SOI MOSFET from TID defects after gamma irradiation. 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS). Published. 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), Caen, France. https://doi.org/10.1109/EuroSOI-ULIS53016.2021.9560673
Article de journal
Sabri Alirezaei, I., André, N., & Flandre, D. (2020). Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology. IEEE Transactions on Electron Devices, 67(11), p. 4641 - 4644. https://doi.org/10.1109/TED.2020.3017699 (Original work published 2020)
Kamel, D., Standaert, F.-X., Duc, A., Flandre, D., & Berti, F. (2020). Learning with Physical Noise or Errors. IEEE Transactions on Dependable and Secure Computing, 17(5), 957-971. https://doi.org/10.1109/TDSC.2018.2830763 (Original work published 2020)
Zeng, X., Zhukova, M., Faniel, S., Proost, J., & Flandre, D. (2020). Structural and Opto‑electronic characterization of CuO thin films prepared by DC reactive magnetron sputtering. Journal of Materials Science: Materials in Electronics, 31, 4563-4573. https://doi.org/10.1007/s10854-020-03007-4 (Original work published 2020)
Zhukova, M., Kotipalli, R., Poncelet, O., Samain, L., Fourdrinier, L., & Flandre, D. (2020). Correlation and optimization of the optoelectrical properties of DC magnetron-sputtered Cu2ZnSnS4 absorber layer as a function of the material composition. Materials Science in Semiconductor Processing, 121(105307), 1-11. https://doi.org/10.1016/j.mssp.2020.105367 (Original work published 2021)
Nyssens, L., Halder, A., Esfeh, B. K., Planes, N., Haond, M., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2020). Self-Heating in FDSOI UTBB MOSFETs at Cryogenic Temperatures and Its Effect on Analog Figures of Merit. I E E E Journal of the Electron Devices Society, 8, 789-796. https://doi.org/10.1109/JEDS.2020.2999632 (Original work published 2020)
Jiang, B., Huang, H., Chen, R., Flandre, D., Wan, D., Chen, X., Xingqiang, L., Cong, Y., & Lei, L. (2020). Black phosphorus field effect transistors stable in harsh conditions via surface engineering. Applied Physics Letters, 117(111602), 111602-1 à 111602-5. https://doi.org/10.1063/5.0021335 (Original work published 2020)
Pampin, R., Raskin, J.-P., Huynen, I., & Flandre, D. (2020). Electrodes-oxide-semiconductor device for biosensing: Renewed conformal analysis and multilayer algorithm. Journal of Electroanalytical Chemistry, 856, 113651. https://doi.org/10.1016/j.jelechem.2019.113651 (Original work published 2020)
Puyol Troisi, R., Molle, Y., Pétré, S., Walewyns, T., Francis, L., & Flandre, D. (2020). A Practical Approach for the Evaluation of Noise in Oscillator-Based Resistive Sensor Interfaces. IEEE Sensors. Proceedings, 1-4. https://doi.org/10.1109/SENSORS47125.2020.9278889 (Original work published 2020)
Stoukatch, S., André, N., Delhaye, T., Dupont, F., Redouté, J.-M., & Flandre, D. (2020). Anisotropic conductive film & flip-chip bonding for low-cost sensor prototyping on rigid & flex PCB. IEEE Sensors, 2020, 1-4. https://doi.org/10.1109/SENSORS47125.2020.9278669 (Original work published 2020)
Galy, P., Soto, F., Bourgeat, J., Jacquier, B., Kilchytska, V., & Flandre, D. (2020). Experimental results on diodes and BIMOS ESD devices in 28 nm FD-SOI under TLP & TID radiation. Microelectronics Reliability, 114, 113938. https://doi.org/10.1016/j.microrel.2020.113938 (Original work published 2020)
Rudenko, T., Nazarov, A., Barraud, S., Kilchytska, V., & Flandre, D. (2020). A method for threshold voltage extraction in junctionless MOSFETs using the derivative of transconductance-to-current ratio. Solid-State Electronics, 107723(161), 26. https://doi.org/10.1016/j.sse.2019.107723 (Original work published 2019)
Alcalde Bessia, F., Flandre, D., André, N., Irazoqui, J., Pérez, M., Gómez Berisso, M., & Lipovetzky, J. (2020). Ultra Low Power Ionizing Dose Sensor Based on Complementary Fully Depleted MOS Transistors for Radiotherapy Application. IEEE Transactions on Nuclear Science, 67(10), 2217-2223. https://doi.org/10.1109/TNS.2019.2945040 (Original work published 2019)
Wan, D., Hao, H., CHEN, C., Abliz, A., Ye, C., Liu, X., Zou, X., Li, G., Flandre, D., & Liao, L. (2020). High Voltage Gain WSe2 Complementary Compact Inverter With Buried Gate for Local Doping. IEEE Electron Device Letters, 41(6), 944-947. https://doi.org/10.1109/LED.2020.2988488 (Original work published 2020)
Gimeno Gasca, C., Flandre, D., Schramme, M., Frenkel, C., & Bol, D. (2020). A 2.24-pJ/bit 2.5-Gb/s UWB receiver in 28-nm FDSOI CMOS for low-energy chip-to-chip communications. A E Ue: International Journal of Electronics and Communication, 114(152996), 8. https://doi.org/10.1016/j.aeue.2019.152996 (Original work published 2020)
Lontchi Jioleo, J., Zhukova, M., Kovacic, M., Krc, J., Chen, W.-C., Edoff, M., Bose, S., Salomé, P. M. P., Goffard, j., Cattoni, A., Gouillart, L., Collin, S., Gusak, V., & Flandre, D. (2020). Optimization of Back Contact Grid Size in Al2O3-Rear-Passivated Ultrathin CIGS PV Cells by 2-D Simulations. I E E E Journal of Photovoltaics, 10(6), 1908-1917. https://doi.org/10.1109/JPHOTOV.2020.3012631 (Original work published 2020)
Schramme, M., Gimeno Gasca, C., Cathelin, A., Flandre, D., & Bol, D. (2020). A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI. IEEE Solid-State Circuits Letters, 3, 478-481. https://doi.org/10.1109/LSSC.2020.3026759 (Original work published 2020)
Nyssens, L., Halder, A., Kazemi Esfeh, B., Planes, N., Flandre, D., Kilchytska, V., & Raskin, J.-P. (2020). 28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K. I E E E Journal of the Electron Devices Society, B, 646-654. https://doi.org/10.1109/JEDS.2020.3002201 (Original work published 2020)
Tounsi, F., Flandre, D., Rufer, L., & Francis, L. (2020). Performances Evaluation of On-chip Large-Size Tapped Transformer for MEMS applications. IEEE Transactions on Instrumentation and Measurement, 69(9), 7051-7060. https://doi.org/10.1109/TIM.2020.2974409 (Original work published 2020)
Papier de conférence
Li, G., He, J., Flandre, D., & Liao, l. (2020). Defect Engineering in n-Type Oxide Semiconductor TFTs. International Conference on Display Technology 2020, Wuhan (China).
Schwarz, M., Koes, A., & Flandre, D. (2020). Schottky-Barrier FET Ultra-Low-Power Diode. Proceedings, p. 1-4. https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365540
Lontchi Jioleo, J., Zhukova, M., Kovacic, M., Krc, J., Chen, W.-C., Edoff, M., Bose, S., Salomé, P., Goffard, J., Cattoni, A., Collin, S., & Flandre, D. (2020). Ultra-thin CIGS: 2D Modelling and impactful results for optimal cell design and characterizations. Proceedings of the 2020 47th IEEE Photovoltaic Specialists Conference (PVSC). 2020 47th IEEE Photovoltaic Specialists Conference (PVSC), Calgary (Canada).
Flandre, D., Schramme, M., Gimeno Gasca, C., Drouguet, M., André, N., Craeye, C., & Bol, D. (2020). Cinq générations de chips UWB (Ultra-Wide-Band) pour la géo-localisation et la transmission de données à très basse consommation. FETCH 2020 - École d’hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes, Montréal (Canada).
Kilchytska, V., Makovejev, S., Kazemi Esfeh, B., Nyssens, L., Halder, A., Raskin, J.-P., & Flandre, D. (2020). Electrical characterization of advanced MOSFETs towards analog and RF applications. Proceedings of the 2020 IEEE Latin America Electron Devices Conference (LAEDC), 4. https://doi.org/10.1109/LAEDC49063.2020.9073536
Amor, S., Van Brandt, L., Kilchytska, V., Machhout, M., Francis, L., & Flandre, D. (2020). Low-frequency noice analysis of on-membrane MOSFET and in-situ thermal annealing. 2020 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS, Virtual event.
Kaziz, S., Maamer, B., Delhaye, T., Tounsi, F., Francis, L., & Flandre, D. (2020). Tuning Range Comparison Between Different Planar Inductors Layouts on PCB. Proceedings of DTS 2020, p. 6.
Puyol Troisi, R., Pétré, S., Danlée, Y., Walewyns, T., Francis, L., & Flandre, D. (2020). Design Considerations of Ultra-Low-Power Polymer Gas Microsensors Based on Noise Analysis. Proceedings of the 4th International Conference nanoFIS 2020—Functional Integrated nano Systems. 4th International Conference nanoFIS 2020—Functional Integrated nano Systems, Graz (Austria).
Wei, P., André, N., Zeng, X., Sabri Alirezaei, I., Li, G., Bouterfa, M., Francis, L., & Flandre, D. (2020). Micrometer-thin SOI Sensors for E-Skin Applications. IEEE Sensors. Proceedings. 2020 IEEE SENSORS, Rotterdam (the Netherlands). https://doi.org/10.1109/SENSORS47125.2020.9278716 (Original work published 2020)
Article de journal
Kovacic, M., Krc, J., Lipovsek, B., Chen, W.-C., Edoff, M., Bolt, P. J., van Deelen, J., Zhukova, M., Lontchi Jioleo, J., Flandre, D., Salomé, P., & Topic, M. (2019). Light management design in ultra-thin chalcopyrite photovoltaic devices by employing optical modelling. Solar Energy Materials & Solar Cells, 200(109933), 9. https://doi.org/10.1016/j.solmat.2019.109933 (Original work published 2019)
Kovačič, M., Krč, J., Lipovšek, B., Chen, W.-C., Edoff, M., Bolt, P. J., van Deelen, J., Zhukova, M., Lontchi Jioleo, J., Flandre, D., Salomé, P., & Topič, M. (2019). Modelling Supported Design of Light Management Structures in Ultra-Thin Cigs Photovoltaic Devices. Informacije MIDEM : journal of microelectronics, electric components and materials, 49(3), 183-190. https://doi.org/10.33180/InfMIDEM2019.307 (Original work published 2019)
Kazemi Esfeh, B., Kilchytska, V., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2019). 28 nm FDSOI nMOSFET RF Figures of Merits and Parasitic Elements extraction at Cryogenic Temperature down to 77 K. I E E E Journal of the Electron Devices Society, 7, 810816. https://doi.org/10.1109/JEDS.2019.2906724 (Original work published 2019)
Kazemi Esfeh, B., Planes N., Haond M., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2019). 28 nm FDSOI analog and RF figures of merit at N2 cryogenic temperatures. Solid-State Electronics, 159(September 2019), 77-82. https://doi.org/10.1016/j.sse.2019.03.039 (Original work published 2019)
Nawaz, K., Van Brandt, L., Levi, I., Standaert, F.-X., & Flandre, D. (2019). A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs. Integration, 2019(68), 71-79. https://doi.org/10.1016/j.vlsi.2019.06.006 (Original work published 2019)
Salerno Galembeck, E. H., Flandre, D., Renaux, C., & Pinillos Gimenez, S. (2019). Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment. Journal of Integrated Circuits and Systems, 14(2), 8. https://doi.org/10.29292/jics.v14i2.34 (Original work published 2019)
Xia, Y., Li, G., Jiang, B., Yang, Z., Liu, X., Xiao, X., Flandre, D., Wang, C., Liu, Y., & Liao, L. (2019). Exploring and Suppressing Kink Effect of Black Phosphorus FieldEffect Transistors Operating in Saturation Regime. Nanoscale, 2019, 9. https://doi.org/10.1039/C9NR02907A (Original work published 2019)
André, N., Rack, M., Nyssens, L., Oueslati, D., Ben Ali, K., Gilet, S., Craeye, C., Raskin, J.-P., & Flandre, D. (2019). Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas. I E E E Journal of the Electron Devices Society, 7, 393397. https://doi.org/10.1109/JEDS.2019.2902636 (Original work published 2019)
Dekimpe, R., Xu, P., Schramme, M., Gérard, P., Flandre, D., & Bol, D. (2019). A Battery-less BLE Smart Sensor for Room Occupancy Tracking Supplied by 2.45-GHz Wireless Power Transfer. Integration, 67, 8-18. https://doi.org/10.1016/j.vlsi.2019.03.006 (Original work published 2019)
Li, G., André, N., Qi Chen, Huiru, W., Francis, L., Zeng, Y., Liao, L., & Flandre, D. (2019). Low-Power, High-Sensitivity Temperature Sensor Based on Ultrathin SOI Lateral p-i-n Gated Diode. IEEE Transactions on Electron Devices, 66(9), 4001-4007. https://doi.org/10.1109/TED.2019.2930244 (Original work published 2019)
Li, G., André, N., Huet, B., Delhaye, T., Reckinger, N., Francis, L., Lioa, L., Raskin, J.-P., Zeng, Y., & Flandre, D. (2019). Enhanced ultraviolet photoresponse in a graphene-gated ultra-thin Sibased photodiode. Journal of Physics D: Applied Physics, 52(24), 7. https://doi.org/10.1088/1361-6463/ab12b8 (Original work published 2019)
Martins d’Oliveira, L., Kilchytska, V., Flandre, D., & de Souza, M. (2019). Self-Cascode Current-Voltage Curve-Construction Algorithm from Single MOSFET Measurements for Analog Figures-of-Merit Extraction. Journal of Integrated Circuits and Systems, 14(1), 6. https://doi.org/10.29292/jics.v14i1.69 (Original work published 2019)
Xu, P., Flandre, D., & Bol, D. (2019). Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors. IEEE Journal of Solid State Circuits, 99, 2717-2729. https://doi.org/10.1109/JSSC.2019.2914581 (Original work published 2019)
Caicedo, N., Leturcq, R., Raskin, J.-P., Flandre, D., & Lenoble, D. (2019). Detection mechanism in highly sensitive ZnO nanowires network gas sensors. Materials science, preprint, 27. (Original work published 2019)
Wang, H., He, J., Xu, Y., André, N., Zeng, Y., Flandre, D., Liao, L., & Li, G. (2019). Impact of hydrogen dopant incorporation on InGaZnO, ZnO and In2O3 thin film transistors. Physical Chemistry Chemical Physics, 2020(22), 1591-1597. https://doi.org/10.1039/C9CP05050G (Original work published 2019)
He, J., Li, G., Lv, Y., Wang, C., Liu, C., Li, J., Flandre, D., Chen, H., Guo, T., & Liao, L. (2019). Defect Self-Compensation for High-Mobility Bilayer InGaZnO/In2O3 Thin-Film Transistor. Advanced Electronic Materials, 5(4), 1900125 (1-7). https://doi.org/10.1002/aelm.201900125 (Original work published 2019)
Papier de conférence
Flandre, D., Kazemi Esfeh, B., Nyssens, L., Halder, A., Kilchytska, V., & Raskin, J.-P. (2019). Figures of merit of nanoscale transistors at cryogenic temperature: 28nm UTBB FD SOI nMOSFET case study. 3rd Symposium on Schottky barrier MOS devices, Gif-sur Yvette (France).
Nyssens, L., Halder, A., Planes, N., Flandre, D., Kilchytska, V., & Raskin, J.-P. (2019). 28 FDSOI RF Figures of Merit down to 4.2 K. IEEE S3S Conference, San Jose (USA).
Bol, D., Schramme, M., Moreau, L., Haine, T., Xu, P., Frenkel, C., Dekimpe, R., Stas, F., & Flandre, D. (2019). A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode. Proceedings of the 2019 IEEE International Solid- State Circuits Conference (ISSCC 2019), 322-323. https://doi.org/10.1109/ISSCC.2019.8662293
Van Brandt, L., Kazemi Esfeh, B., Kilchytska, V., & Flandre, D. (2019). Robust Methodology for Low-Frequency Noise Power Analyses in Advanced MOS Transistors. 5th joint EUROSOI – ULIS 2019 Conference, Grenoble (France).
Martínez-Pérez, A. D., Gimeno Gasca, C., Flandre, D., Aznar, F., Royo, G., & Sánchez-Azqueta, C. (2019). Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA. Proceedings of SMACD 2019. Accepted/in-press. SMACD-16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Lausanne (Suisse). https://doi.org/10.1109/SMACD
Martínez Pérez, A. D., Gimeno Gasca, C., Flandre, D., Aznar, F., Royo, G., Azqueta, C. S., & Celma, S. (2019). Metodología de optimización para LNA de cancelación de ruido y distorsión. VIII JORNADA DE JÓVENES INVESTIGADORES DEL I3A, Zaragoza (Spain).
Nyssens, L., Halder, A., Kazemi Esfeh, B., Planes, N., Haond, M., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2019). Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures. 49th European Solid-State Device Research Conference (ESSDERC 2019), Cracow (Poland).
Flandre, D., André, N., Delhaye, T., Francis, L., & Raskin, J.-P. (2019). Capteurs CMOS physiques & physiologiques flexibles et basse consommation. Ecole d’hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2019), Louvain-la-Neuve (Belgium).
Pétré, S., Walewyns, T., Fomekong, R. L., Lahem, D., Debliquy, M., Flandre, D., & Francis, L. (2019). Live Demonstration: A Highly Selective Temperature and Humidity Compensated MOX Based Multi-Gas Sensor Module with Bluetooth 5.0 Connectivity. Proceedings of IEEE Sensors 2019. Published. 2019 IEEE SENSORS, Montréal (Canada).
Delhaye, T., Ge, C., Francis, L., Cretu, E., & Flandre, D. (2019). One-Day Fast-Prototyping Process for Functionalized Membrane Array on Flexible Substrate. 45th International Conference on Micro & Nano Engineering, Rhodes (Greece).
Rudenko, T., Nazarov, A., Barraud, S., Kilchytska, V., & Flandre, D. (2019). gm/ID-derivative Method for Threshold Voltage Extraction in Junctionless MOSFETs. 5th joint EUROSOI – ULIS 2019 Conference, Grenoble (France).
Martins d’Oliveira, L., Kilchytska, V., Planes, N., Flandre, D., & de Souza, M. (2019). Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs. IEEE S3S Conference, San Jose (USA).
Martins d’Oliveira, L., Kilchytska, V., Flandre, D., & de Souza, M. (2019). Harmonic Distortion in Symmetric and Asymmetric Self-Cascodes of UTBB FD SOI Planar MOSFETs. 2019 34th Symposium on Microelectronics Technology and Devices (SBMICRO), Sao Paulo (Brazil).
Martínez, A., Alvarado, J., Kilchytska, V., Alcántara, S., & Flandre, D. (2019). Back-gate bias Effect on the MOSFET-C CMOS UTBB Performance by Circuit Simulations. 5th joint EUROSOI – ULIS 2019 Conference, Grenoble (France).
Zhukova, M., Kotipalli, R., Poncelet, O., Samain, L., Fourdrinier, L., & Flandre, D. (2019). Optimization of optoelectrical properties of DC magnetron sputtered Cu 2 ZnSnS 4 absorber layer. E-MRS 2019(European Materials Research Society) - Spring Meeting 2019, Acropolis Congress Center Nice (France).
Anton Köck, Bol, D., Flandre, D., & et al. (2019). 3D-Integrated Multi-Sensor Demonstrator System for Environmental Monitoring. IEEE Solid-State Sensor and Actuator Workshop. Technical Digest, 2019, 1136-1139. (Original work published 2019)
Van Brandt, L., Kazemi Esfeh, B., Planes, N., Kilchytska, V., & Flandre, D. (2019). Low-Frequency Noise Transistor Performance for UTBB FDSOI MOSFET-C Filters. S3S Conference, San José (USA).
Delhaye, T., Ge, C., Francis, L., Flandre, D., & Cretu, E. (2019). Macro-Modeling Library in Simscape for MEMS Pressure Sensors Based on Energy-Flow Paradigm. Proceedings of the conference Design, Test, Integration & Packaging of MEMS/MOEMS. Published. Design, Test, Integration & Packaging of MEMS/MOEMS, Paris (France). https://doi.org/10.1109/DTIP.2019.8752962
Article de journal
Garud, S., Gampa, N., Allen, T. G., Kotipalli, R., Flandre, D., Batuk, M., Hadermann, J., Meuris, M., Poortmans, J., Smets, A., & Vermang, B. (2018). Surface Passivation of CIGS Solar Cells Using Gallium Oxide. Physica Status Solidi. A: Applications and Materials Science (Print), 215(1700826), 6. https://doi.org/10.1002/pssa.201700826 (Original work published 2018)
Gammon, P. M., Chan, C. W., Li, F., Gity, F., Trajkovic, T., Pathirana, V., Flandre, D., & Kilchytska, V. (2018). Development, characterisation and simulation of wafer bonded Si-on-SiC substrates. Materials Science in Semiconductor Processing, 78, 69-74. https://doi.org/10.1016/j.mssp.2017.10.020 (Original work published 2018)
Gimeno Gasca, C., Bol, D., & Flandre, D. (2018). Multilevel Half-Rate Detector for Clock and Data Recovery Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5. https://doi.org/10.1109/TVLSI.2018.2826440 (Original work published 2018)
Li, G., Abliz, A., Xu, L., André, N., Liu, X., Zeng, Y., Flandre, D., & Liao, L. (2018). Understanding hydrogen and nitrogen doping on active defects in amorphous In-Gas-Zn-O thin-film transistors. Applied Physics Letters, 112(253504), 5. https://doi.org/10.1063/1.5032169 (Original work published 2018)
Haddad, P.-A., Flandre, D., & Raskin, J.-P. (2018). Intrinsic rectification in common-gated graphene field-effect transistors. Nano Energy, 43, 37-46. https://doi.org/10.1016/j.nanoen.2017.10.049 (Original work published 2018)
Gimeno Gasca, C., Flandre, D., & Bol, D. (2018). Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 65(6), 2015-2023. https://doi.org/10.1109/TCSI.2017.2765312 (Original work published 2018)
Kamel, D., Standaert, F.-X., Duc, A., Flandre, D., & Berti, F. (2018). Learning with Physical Noise or Errors. IEEE Transactions on Dependable and Secure Computing, 14. (Original work published 2018)
Alves, C. R., Flandre, D., & de Souza, M. (2018). Analysis of Mismatching on the Analog Characteristics of GC SOI MOSFETs. Journal of Integrated Circuits and Systems, 13(3), 1-8. https://doi.org/10.29292/jics.v13i3.16 (Original work published 2018)
Assalti, R., Flandre, D., & de Souza, M. (2018). Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs. Journal of Integrated Circuits and Systems, 13(2), 1-7. https://doi.org/10.29292/jics.v13i2.15 (Original work published 2018)
Müller, A., Vu, X. T., Pachauri, V., Francis, L., Flandre, D., & Ingebrandt, S. (2018). Wafer-Scale Nanoimprint Lithography Process Towards Complementary Silicon Nanowire Field-Effect Transistors for Biosensor Applications. Physica Status Solidi. A: Applied Research, 1800234, 10. https://doi.org/10.1002/pssa.201800234 (Original work published 2018)
Papier de conférence
Dekimpe, R., Xu, P., Schramme, M., Flandre, D., & Bol, D. (2018). A Battery-less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer. 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018), Platja d’Aro (Spain).
Restani Alves, C., de Souza, M., & Flandre, D. (2018). Numerical Simulation and Analysis of Transistor Channel Length and Doping Mismatching in GC SOI nMOSFETs Analog Figures of Merit. Proceedings of SBMicro 2018. Published. 2018 33rd Symposium on Microelectronics Technology and devices (SBMicro 2018), Bento Gonçalves, Rio Grande do Sul (Brazil ). (Original work published 2018)
Saoutieff, E., Faucon, A., Boisseau, S., Ernst, T., Policheti, T., Miglietta, M. L., Alfano, B., Massera, E., De Vito, S., Pétré, S., Walewyns, T., André, N., Flandre, D., Moldovan, C., Dinulescu, S., Greitans, M., & Romani, A. (2018). Sensors platform for health and environmental monitoring. Proceedings of the Workshop Nano2sense 2018. Accepted/in-press. Workshop Nano2sense, Grenoble (France). (Original work published 2018)
Kazemi Esfeh, B., Masselus, M., Planes, N., Haond, M., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2018). 28 FDSOI Analog and RF Figures of merit at Cryogenic Temperatures. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon EUROSOI-ULIS 2018, Granada (Spain).
Nawaz, K., Levi, I., Standaert, F.-X., & Flandre, D. (2018). A Transient Noise Analysis of Secured Dual-rail based Logic Style. 2nd New Generation of Circuits & Systems Conference (NGCAS 2018), Valetta (Malta).
Gimeno Gasca, C., Flandre, D., & Bol, D. (2018). Low-Power Half-Rate Dual-Loop Clock-Recovery System in 28-nm FDSOI. 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS 2018), Puerto Vallarte (Mexico).
Nawaz, K., Van Brandt, L., Standaert, F.-X., & Flandre, D. (2018). Let’s make it Noisy: A Simulation Methodology for adding Intrinsic Physical Noise to Cryptographic Designs. 14th Conference on PhD Research in Microelectronics and Electronics, Prague (Czech Republic).
Vono Peruzzi, V., da Silva, G. A., Renaux, C., Flandre, D., & Pinillos Gimenez, S. (2018). Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs. Proceedings of SBMicro 2018. Published. 2018 33rd Symposium on Microelectronics Technology and devices (SBMicro 2018), Bento Gonçalves, Rio Grande do Sul (Brazil ). (Original work published 2018)
Assalti, R., de Souza, M., & Flandre, D. (2018). Linearity enhancement in asymmetric self-cascode composed by FD SOI nMOSFETs. Proceedings of SBMicro 2018. Published. 2018 33rd Symposium on Microelectronics Technology and devices (SBMicro 2018), Bento Gonçalves, Rio Grande do Sul, Brazil. (Original work published 2018)
Haine, T., Segers, J., Flandre, D., & Bol, D. (2018). Gradient Importance Sampling: an Efficient Statistical Extraction methodology of High-Sigma SRAM Dynamic Characteristics. 2018 Design, Automation Test in Europe Conference Exhibition, 195-200. https://doi.org/10.23919/DATE.2018.8342002
Bessia, F. A., Flandre, D., André, N., Irazoqui, J., Pérez, M., Berisso, M. G., & Lipovetzky, J. (2018). Fully Depleted SOI MOSFET Sensors in Accumulation-mode for Total Dose Measurement. 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference, Sydney (Australia).
Flandre, D., André, N., Delhaye, T., Walewyns, T., & Francis, L. (2018). Wearable physical & physiological low-power sensors. proceedings of the ESSDERC-ESSCIRC Conference 2018, 18.
Amor, S., Kilchytska, V., André, N., Li, G., Rebey, A., Francis, L., & Flandre, D. (2018). On-membrane PD SOI MOSFET with micro-heater for TID in-situ annealing: experiments versus Eldo and Atlas simulations. Proceedings of SERESSA 2018, 1.
Kamel, D., Bellizia, D., Standaert, F.-X., Flandre, D., & Bol, D. (2018). Demonstrating an LPPN Processor (Short Paper). Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security (ASHES@CCS 2018), p. 18-23. https://doi.org/10.1145/3266444.3266445
Haine, T., Flandre, D., & Bol, D. (2018). An 8-T ULV SRAM macro in 28nm FDSOI with 7.4 pW/bit retention power and back-biased-scalable speed/energy trade-off. IEEE S3S Conference, San Francisco (USA).
Martins d’Oliveira, L., de Souza, M., Kilchytska, V., & Flandre, D. (2018). Design Benefits of Self-Cascode Configuration for Analog Applications in 28nm FDSOI technology. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon EUROSOI-ULIS 2018, Granada (Spain).
Xu, P., Flandre, D., & Bol, D. (2018). Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors. Proceedings of the IEEE Asian Solid-State Circuits Conference, 107-110.
Kazemi Esfeh, B., Kilchytska, V., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2018). 28 FDSOI RF Figures of Merits and Parasitic Elements at Cryogenic Temperature. Proceedings of the IEEE S3S Conference, 2.
Martins d’Oliveira, L., de Souza, M., Kilchytska, V., & Flandre, D. (2018). Asymmetric Self-Cascode Current-Voltage Constructing Algorithm for Analog Figures-of-Merit Extraction. proceedings of SBMicro 2018. Published. 2018 33rd Symposium on Microelectronics Technology and devices (SBMicro 2018), Bento Gonçalves, Rio Grande do Sul (Brazil ). (Original work published 2018)
Brevet
Poncelet, O., Flandre, D., Kotipalli, R. V. R., & Crahay, A. (2018). METHOD FOR PRODUCING IMPROVED BLACK SILICON ON A SILICON SUBSTRATE.
Article de journal
Galembeck, E. H. S., Renaux, C., Flandre, D., Finco, S., & Gimenez, S. P. (2017). Boosting the SOI MOSFET Electrical Performance by Using the Octogonal Layout Style in High Temperature Environment. IEEE Transactions on Device and Materials Reliability, 17(1), 1-8. https://doi.org/10.1109/TDMR.2017.2652729 (Original work published 2017)
Aguirre, J., Bol, D., Flandre, D., Sanchez-Azqueta, C., & Celma, S. (2017). A robust 10 Gbps duobinary transceiver in 0.13 μm SOI CMOS for short-haul optical networks. IEEE Transactions on Industrial Electronics, 99, 1. https://doi.org/10.1109/TIE.2017.2716870 (Original work published 2017)
Assalti, R., Trevidoli Dorai, R., Flandre, D., & de Souza, M. (2017). Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs. Journal of Integrated Circuits and Systems, 12, 62-70. (Original work published 2017)
Sedki, A., André, N., Kilchytska, V., Tounsi, F., Mezghani, B., Gérard, P., Ali, Z., Udrea, F., Flandre, D., & Francis, L. (2017). In-situ Thermal Annealing of On-Membrane SOI Semiconductor-Based Devices After High Gamma Dose irradiation. Nanotechnology, 28(18), 16. https://doi.org/10.1088/1361-6528/aa66a4 (Original work published 2017)
Poncelet, O., Kotipalli, R. V. R., Vermang, B., Macleod, A., Francis, L., & Flandre, D. (2017). Optimisation of rear reflectance in ultra-thin CIGS solar cells towards >20% efficiency. Solar Energy, 146, 443-452. https://doi.org/10.1016/j.solener.2017.03.001 (Original work published 2017)
Li, G., Kilchytska, V., André, N., Francis, L., Zeng, Y., & Flandre, D. (2017). Leakage Current and Low-Frequency Noise Analysis and reduction in a Suspended SOI Lateral p-i-n Diode. IEEE Transactions on Electron Devices, 8. https://doi.org/10.1109/TED.2017.2742863 (Original work published 2017)
Li, G., André, N., Gérard, P., Zeeshan Ali, S., Udrea, F., Francis, L., Zeng, Y., & Flandre, D. (2017). Multiple-Wavelength Detection in SOI Lateral PIN Diodes with Backside Reflectors. IEEE Transactions on Industrial Electronics, 10. https://doi.org/10.1109/TIE.2017.2694393 (Original work published 2017)
Pereira, A. S. N., de Streel, G., Planes, N., Haond, M., Giacomini, R., Flandre, D., & Kilchytska, V. (2017). An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models. Solid-State Electronics, 128, 67-71. https://doi.org/10.1016/j.sse.2016.10.017 (Original work published 2016)
Gammon, P. M., Li, F., Chan, C. W., Sanchez, A., Hindmarsh, S., Gity, F., Trajkovic, T., Kilchytska, V., Pathirana, V., Camuso, G., Ben Ali, K., Flandre, D., Mawby, P. A., & Gardner, J. W. (2017). The Effect of Interfacial Charge on the Development of Wafer Bonded Silicon-on-Silicon-Carbide Power Devices. Materials Science Forum, 897, 747-750. https://doi.org/10.4028/www.scientific.net/MSF.897.747 (Original work published 2017)
Kazemi Esfeh, B., Makovejev, S., Basso, D., Desbonnets, E., Kilchytska, V., Flandre, D., & Raskin, J.-P. (2017). RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers. Solid-State Electronics, 128(February 2017), 121-128. https://doi.org/10.1016/j.sse.2016.10.035 (Original work published 2017)
Haddad, P.-A., Flandre, D., & Raskin, J.-P. (2017). A Quasi-Static Model of Silicon Substrate Effects in Graphene Field Effect Transistors. IEEE Electron Device Letters, 38(7), 987-990. https://doi.org/10.1109/LED.2017.2706362 (Original work published 2017)
Novo, C., Bühler, R., Giacomini, R., Afzalian, A., & Flandre, D. (2017). Quantum Efficiency Improvement of SOI PIN Lateral Diodes Operating as UV Detectors at High Temperatures. IEEE Sensors Journal, PP(99), 8. https://doi.org/10.1109/JSEN.2017.2647848 (Original work published 2017)
Doria, R. T., Flandre, D., Trevisoli, R., De Souza, M., & Pavanello, M. A. (2017). Effect of the back bias on the analog performance of standard FD and UTBB transitors-based self-cascode Structures. Semiconductor Science and Technology, 32, 1. https://doi.org/10.1088/1361-6641/aa7659 (Original work published 2017)
Kotipalli, R. V. R., Poncelet, O., Li, G., Zeng, Y., Francis, L., Vermang, B., & Flandre, D. (2017). Adressing the impact of rear surface passivation mechanisms on ultra-thin Cu(In,Ga)Se2 solar cells performances using SCAPS 1-D model. Solar Energy, 157, 603-613. https://doi.org/10.1016/j.solener.2017.08.055 (Original work published 2017)
Amor, S., André, N., Gérard, P., Ali, S. Z., Udrea, F., Tounsi, F., Mezghani, B., Francis, L., & Flandre, D. (2017). Reliable characteristics and stabilization of on-membrane SOI MOSFET-based components heated up to 335 °C. Semiconductor Science and Technology, 32(1), 9. https://doi.org/10.1088/1361-6641/32/1/014001 (Original work published 2016)
Papier de conférence
Assalti, R., de Souza, M., & Flandre, D. (2017). Channel Width Influence on the Analog Performance of the Asymmetric Self-Cascode FD SOI nMOSFETs. Proceedings of the 32nd Symposium on Microelectronics Technology and Devices (SBMicro 2017). Published. 32nd Symposium on Microelectronics Technology and Devices (SBMicro 2017), Fortaleza (Brazil).
Kilchytska, V., Kazemi Esfeh, B., Gimeno Gasca, C., Parvais, B., Planes, N., Hahond, M., Raskin, J.-P., & Flandre, D. (2017). Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs. Proceedings of 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon – ULIS, p. session 10, paper # 1. https://doi.org/10.1109/ULIS.2017.7962581
Van Brandt, L., Kilchytska, V., Raskin, J.-P., Parvais, B., & Flandre, D. (2017). Optimal measurement parameters for accurate time-domain and spectral analyses of RTN. 47th IEEE European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium.
Haddad, P.-A., Flandre, D., & Raskin, J.-P. (2017). Intrinsic rectification in gated CVD graphene ribbons. Proceedings of Graphene Barcelona 2017, p. paper #19.
Nawaz, K., Kamel, D., Standaert, F.-X., & Flandre, D. (2017). Scaling Trends for Dual-Rail Logic Styles against Side-Channel Attacks: a Case-Study. In Sylvain Guilley (ed.), Proceedings of the 8th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2017) (p. p. 19-33). Springer.
Delhaye, T., André, N., Gilet, S., Gimeno Gasca, C., Francis, L., & Flandre, D. (2017). High-Efficiency Wireless Power Transfer for mm-Size Biomedical Implants (slides). 2017 IEEE Sensors Conference, Glasgow (Schotland).
André, N., Delhaye, T., Al Kadi Jazairli, M., Olbrechts, B., Gérard, P., Francis, L., Raskin, J.-P., & Flandre, D. (2017). Ultra-low-power SOI CMOS pressure sensor based on orthogonal PMOS gauges. 22nd IMEKO TC4 International Symposum & 20th International Workshop on ADC Modelling and Testing, Iasi (Romania).
Kazemi Esfeh, B., Kilchytska, V., Parvais, B., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2017). Back-gate bias effect on 3-port UTBB-FDSOI non-linearity performance. proceedings of ESSDERC 2017. Published. 2017 47th European Solid-State Device Research Conference (ESSDERC 2017), Leuven (Belgium). https://doi.org/10.1109/ESSDERC.2017.8066613 (Original work published 2017)
Peruzzi, V. V., Renaux, C., Flandre, D., & Gimenez, S. P. (2017). Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style. 2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro 2017), Fortaleza (Brazil).
Restani Alves, C., Pavanello, M. A., de Souza, M., & Flandre, D. (2017). Experimental Evaluation of Mismatching on the Analog Characteristics of GC SOI MOSFETs. Proceedings of the 32nd Symposium on Microelectronics Technology and Devices (SBMicro 2017). Published. 32nd Symposium on Microelectronics Technology and Devices (SBMicro 2017), Fortaleza (Brazil).
Gimeno Gasca, C., Bol, D., & Flandre, D. (2017). SOI, from Basics to Applications. International Microwave Symposium (IMS 2017), Honolulu (Hawai).
Kazemi Esfeh, B., Kilchytska, V., Parvais, B., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2017). Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and Parasitic Elements. Proceedings of EUROSOI-ULIS 2017. Published. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2017), Athens (Greece). https://doi.org/10.1109/ULIS.2017.7962569 (Original work published 2017)
Doria, R. T., Trevisoli, R., de Souza, M., Pavanello, M. A., & Flandre, D. (2017). Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors. Proceedings of the 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). Published. 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, California (USA ). https://doi.org/10.1109/S3S.2016.7804387
Haddad, P.-A., Raskin, J.-P., & Flandre, D. (2017). Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS. Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 508-511. https://doi.org/10.1109/ICECS.2016.7841250
Flandre, D., André, N., Al Kadi Jazairli, M., Olbrechts, B., Gilet, S., Haddad, P.-A., Gimeno Gasca, C., & Raskin, J.-P. (2017). vers des capteurs implantés de quelques mm³ à consommation ultra faible, avec transmissions de puissance en RF et de données en UWB. Ecole d’hiver francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH 2017), Québec (Canada).
Flandre, D., Kilchytska, V., Gimeno Gasca, C., Bol, D., Kazemi Esfeh, B., & Raskin, J.-P. (2017). Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers. MOS-AK Workshop, Leuven (Belgium).
Gammon, P. M., Li, F., Chan, C. W., Gity, F., Trajkovic, T., Kilchytska, V., Pathirana, V., Udugampola, N., Ben Ali, K., & Flandre, D. (2017). Design and fabrication of a novel power Si/SiC LDMOSFET for high temperature applications. Proceedings of the 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EU, p. 2.
Gimeno Gasca, C., Stas, F., de Streel, G., Bol, D., & Flandre, D. (2017). Improving Noise and Linearity of CMOS Wideband Inductorless Balun LNAs for 10-GHz Software-Defined Radios in 28nm FDSOI. Proceedings of the 2017 IEEE S3S Conference, p. 2.
Haddad, P.-A., Stas, F., Raskin, J.-P., Bol, D., & Flandre, D. (2017). Automated Layout-integrated Sizing of a 2.45 GHz Differential-Drive Rectifier in 28 nm FDSOI CMOS. Proceedings of the 2017 IEEE Wireless Power Transfer Conference (WPTC 2017). Published. 2017 IEEE Wireless Power Transfer Conference (WPTC 2017), Taipei (Taiwan). https://doi.org/10.1109/WPT.2017.7953845
Ben Ali, K., Gammon, P. M., Chan, C. W., Li, F., Pathirana, V., Trajkovic, T., Gity, F., Flandre, D., & Kilchytska, V. (2017). Single Event Effects and Total Ionising Dose in 600V Si-on-SiC LDMOS Transistors for Rad-Hard Space Applications. Proceedings of the 2017 47th European Solid-State Device Research Conference (ESSDERC), p. 6.
Gammon, P. M., Chan, C. W., Gity, F., Trajkovic, T., Kilchytska, V., Fan, L., Pathirana, V., Camuso, G., Ben Ali, K., Flandre, D., Mawby, P. A., & Gardner, J. W. (2017). Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications. Proceedings of the 11th European Space Power Conference. Published. 11th European Space Power Conference, Thessaloniki (Greece). https://doi.org/10.1051/e3sconf/20171612003
Haine, T., Nguyen, Q.-K., Stas, F., Moreau, L., Flandre, D., & Bol, D. (2017). An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. 43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017), Leuven (Belgium).
Zhukova, M., Kotipalli, R. V. R., Samain, L., Fourdrinier, L., & Flandre, D. (2017). Characterisation and simulation of Cu2ZnSnS4 absorber layers fabricated by sequential DC magnetron sputtering and rapid thermal processingG. proceedings of the 33rd European PV Solar Energy Conference and Exhibition, 6.
Delhaye, T., André, N., Gilet, S., Gimeno Gasca, C., Francis, L., & Flandre, D. (2017). High-Efficiency Wireless power Transfer for mm-Size Biomedical Implants. Proceedings of the 2017 IEEE Sensors Conference. Published. 2017 IEEE Sensors Conference, Glasgow (United Kingdom).
Francis, L., Sedki, A., André, N., Kilchytska, V., Gérard, P., Ali, Z., Udrea, F., & Flandre, D. (2017). A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation. proceedings of ANIMMA 2017, p. 4. https://doi.org/10.1051/epjconf/201817001006
Tang, X., Debliquy, M., Lahem, D., Flandre, D., André, N., Walewyns, T., Francis, L., & Raskin, J.-P. (2017). A hybrid graphene-metal oxide sensor for formaldehyde detection at room temperature. 2016 13th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2016), Beijing (China).
Papier de conférence
Haine, T., Stas, F., de Streel, G., Gimeno Gasca, C., Flandre, D., & Bol, D. (2016). CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. 10th International Conference on Distributed Smart Camera (ICDSC ’16), Paris (France).
Pereira, A. S. d. N., de Streel, G., Planes, N., Haond, M., Giacomini, R., Flandre, D., & Kilchytska, V. (2016). Analysis and modelling of Temperature Effect on DIBL in UTBB FD SOI MOSFETs. Proceedings de la conférence EUROSOI-ULIS 2016, 116-119. https://doi.org/10.1109/ULIS.2016.7440066
Assalti, R., Doria, R. T., Pavanello, M. A., de Souza, M., & Flandre, D. (2016). Low-frequency noise in asymmetric self-cascode FD SOI. 31st Symposium on Microelectronics and Devices (SBMicro 2016), Sao Paulo (Brazil).
Haddad, P.-A., Raskin, J.-P., & Flandre, D. (2016). Automated design of a 13.56 MHz Corner-robust Efficient Differential Drive Rectifier for 10 μA load. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montréal (Canada).
Kazemi Esfeh, B., Kilchytska, V., Flandre, D., & Raskin, J.-P. (2016). RF SOI CMOS Technology on 1st and 2nd Generation Trap-Rich High Resistivity SOI Wafers. Proceedings de la conférence EUROSOI-ULIS 2016, 159-161. https://doi.org/10.1109/ULIS.2016.7440077
Zhukova, M., André, N., Walewyns, T., & Flandre, D. (2016). Micro System Analyzer: Application at UCL. 2016 POLYTEC Conference, Antwerpen (Belgium).
Francis, L., André, N., Amor, S., Gérard, P., Flandre, D., & Udrea, F. (2016). Impact of Radiations on CMOS-MEMS Sensors and a Mitigation Technique. Emerging Technologies CMOS 2016, Montréal (Canada).
Tang, X., Debliquy, M., Lahem, D., Flandre, D., André, N., Walewyns, T., Francis, L., & Raskin, J.-P. (2016). A hybrid graphene-metal oxide sensor for formaldehyde detection at room temperature. 2016 13th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2016), Beijing (China).
Li, G., André, N., Poncelet, O., Gérard, P., Zeeshan Ali, S., Udrea, F., Francis, L., Zeng, Y., & Flandre, D. (2016). Operation of suspended lateral SOI PIN photodiode with aluminium back gate. Proceedings de la conférence EUROSOI-ULIS 2016, 155-158. https://doi.org/10.1109/ULIS.2016.7440076
Peruzzi, V. V., Renaux, C., Flandre, D., & Gimenez, S. P. (2016). Boosting the MOSFETs matching by using diamond layout style. 31st Symposium on Microelectronics Technology and Devices (SBMicro), Salvador (Brazil).
Molto, A. R., Doria, R. T., de Souza, M., Flandre, D., & Pavanello, M. A. (2016). Low-frequency noise of submicron graded-channel SOI nMOSFETs at high temperature. 31st Symposium on Microelectronics Technology and Devices (SBMicro), Salvador (Brazil).
de Souza, M., Pavanello, M. A., & Flandre, D. (2016). Low power highly linear temperature sensor based on SOI lateral PIN diodes. 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame (USA).
Kamel, D., de Streel, G., Merino Del Pozo, S., Nawaz, K., Standaert, F.-X., Flandre, D., & Bol, D. (2016). Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers. In Claude Carlet, M. Anwar Hasan, Vishal Saraswat (ed.), Proceedings of the 6th International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE 2016) (p. p. 233-248). Springer. https://doi.org/10.1007/978-3-319-49445-6_13
André, N., Li, G., Pollissard-Quatremère, G., Couniot, N., Gérard, P., Ali, Z., Udrea, F., Zeng, Y., Francis, L., & Flandre, D. (2016). SOI Sensing Platforms for Water Vapour and Light Detection. CMOSET Conference, Session C5, Montréal (Canada).
Article de journal
Vanzieleghem, T., Couniot, N., Herman-Bausier, P., Flandre, D., Dufrêne, Y., & Mahillon, J. (2016). Role of ionic strength in staphylococcal cell aggregation. Langmuir : the A C S journal of surfaces and colloids, 32(29), 7277-7283. https://doi.org/10.1021/acs.langmuir.6b00499 (Original work published 2016)
Couniot, N., Afzalian, A., Van Overstraeten, N., Francis, L., & Flandre, D. (2016). Capacitive biosensing of bacterial cells: sensitivity optimization. IEEE Sensors Journal, 16(3), 11 pages. https://doi.org/10.1109/JSEN.2015.2485120 (Original work published 2016)
Haddad, P.-A., Gosset, G., Raskin, J.-P., & Flandre, D. (2016). Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load. IEEE Journal of Solid State Circuits, 51(5), 12. https://doi.org/10.1109/JSSC.2016.2527714 (Original work published 2015)
Pavanello, M. A., de Souza, M., Ribeiro, T. A., Martino, J. A., & Flandre, D. (2016). Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature. Semiconductor Science and Technology, 31(11), 114005. https://doi.org/10.1088/0268-1242/31/11/114005 (Original work published 2016)
Kotipalli, R. V. R., Descamps, P., Delamare, R., Kaiser, V., Beaucarne, G., & Flandre, D. (2016). Electronic properties of negatively charged SiOx films deposited by Atmospheric Pressure Plasma Liquid Deposition for surface passivation of p-type c-Si solar cells. Thin Solid Films, 611, 74-77. https://doi.org/10.1016/j.tsf.2016.05.016 (Original work published 2016)
Trevisoli, R., de Souza, M., Trevisoli Doria, R., Kilchytska, V., Flandre, D., & Pavanello, M. A. (2016). Junctionless nanowire transistors operation at temperatures down to 4.2 K. Semiconductor Science and Technology, 31(11), 114001. https://doi.org/10.1088/0268-1242/31/11/114001 (Original work published 2016)
Assalti, R., Martins d’Oliveira, L., Pavanello, M. A., Flandre, D., & de Souza, M. (2016). Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors. IET Circuits, Devices and Systems, 1-7. https://doi.org/10.1049/iet-cds.2015.0159 (Original work published 2015)
Li, G., André, N., Poncelet, O., Gérard, P., Ali, S. Z., Udrea, F., Francis, L., Zeng, Y., & Flandre, D. (2016). Silicon-on-Insulator Photodiode on Micro-Hotplate Platform with Improved Responsivity and High-Temperature Application. IEEE Sensors Journal, PP(99), 9. https://doi.org/10.1109/JSEN.2016.2530020 (Original work published 2016)
Chapitre de livre
Udrea, F., Li, G., Zeng, Y., André, N., Pollissard, G., Francis, L., Flandre, D., Racz, Z., Gardner, J., Zeeshan, A., Buiu, O., Serban, B. C., Cobianu, C., & Wotherspoon, T. (2016). Sensors and Sensor Systems for Harsh Environment Applications. In Kirsten Weide-Zaage, Malgorzata Chrzanowska-Jeske, Krzysztof Iniewski (ed.), Semiconductor Devices in Harsh Environment (p. p. 87-109). Taylor & francis Group. https://doi.org/10.1201/9781315368948-6
Papier de conférence
Dorai, R. T., Flandre, D., Trevisoli, R., de Souza, M., & Pavanelo, M. A. (2015). Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures. Proceedings of SBMicro 2015. Published. 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro), Salvador. https://doi.org/10.1109/SBMicro.2015.7298134
Taha Elthakeb Naguib Youssef, A., Haine, T., Flandre, D., Ismail, Y., Elhamid, H. A., & Bol, D. (2015). Analysis and Optimization for Dynamic Read Stability in 28nm SRAM Bitcells. Proceedings of ISCAS 2015, 14141417. https://doi.org/10.1109/ISCAS.2015.7168908
Bol, D., Boufouss, E. H., Flandre, D., & De Vos, J. (2015). A 0.48mm² 5µW-10mW Indoor-Outdoor PV Energy-Harvesting Management Unit in a 65nm SoC based on a Single Bidirectional Multi-Gain/Multi-Mode Switched-Cap Converter with Supercap Storage. Proceedings of ESSCIRC 2015, 4.
Kazemi Esfeh, B., Kilchytska, V., Barral, V., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2015). Comparative study of effect of parasitic elements on RF FoM in 28 nm FD SOI and Bulk technologies. IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference – S3S’15, paper 7.a.3. https://doi.org/10.1109/S3S.2015.7333532
Couniot, N., Francis, L., & Flandre, D. (2015). An Integrated Capacitive Array Biosensor for the Selective and Real-Time Detection of Whole Bacterial Cells. Proceedings of I3S 2015. Published. 4th International Symposium on Sensor Science (I3S 2015), Bâle (Suisse).
André, N., Pollissard, G., Couniot, N., Gérard, P., Ali, Z. S., Udrea, F., Francis, L., & Flandre, D. (2015). Silicon-on-insulator micro-hotplates platforms for humidity sensing: follow-up of the air quality intercomparison exercise. 3rd International Workshop EuNetAir, Riga (Lettonie).
Flandre, D., Kilchytska, V., Bol, D., Francis, L., André, N., & Raskin, J.-P. (2015). Analog/RF, sensors and MEMS in SOI: demos and performance assessment. SOI Workshop, Dresden (Germany).
Fino, L. N. d. S., da Silveira, M. A. G., Renaux, C., Flandre, D., & Gimenez, S. P. (2015). OCTO Layout Variations as an Alternative to Mitigate TID Effects. 10th Workshop on Semiconductors and Micro & Nano Technology (SEMINATEC 2015), Sao Bernardo do Campo (Brazil).
de Streel, G., Flandre, D., Dehollain, C., & Bol, D. (2015). Towards Ultra-Low-Voltage Wideband Noise-Cancelling LNAs in 28nm FDSOI. Proceedings of IEEE S3S, 2. https://doi.org/10.1109/S3S.2015.7333487
Makovejev, S., Planes, N., Haond, M., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2015). Self-Heating in 28 nm Bulk and FDSOI. Proceedings of EUROSOI-ULIS 2015, 41-44. https://doi.org/10.1109/ULIS.2015.7063768
Zhukova, M., Kotipalli, R. V. R., Samain, L., Fourdrinier, L., & Flandre, D. (2015). Substrate influence on electrical properties of the Mo back contact for thin-film solar cell. 12th NanoWal meeting 2015 - The “Materials, Interfaces and nanostructures” Doctoral school, Mons (Belgium).
Makovejev, S., Planes, N., Haond, M., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2015). Self-heating in 28 nm Bulk and FD SOI. 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon - EUROSOI-ULIS 2015, 41-44.
Bol, D., de Streel, G., & Flandre, D. (2015). Can We Connect Trillions of IoT Sensors in a Sustainable Way ?A Technology/Circuit Perspective. Proceedings of S3S 2015. Published. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2015), Rohnert Park, California (USA).
d’Oliveira, L. M., Doria, R. T., Pavanelo, M. A., Flandre, D., & de Souza, M. (2015). Effect of channel doping concentration on the harmonic distortion of asymmetric n- and p-type self-cascode MOSFETs. Proceedings of SBMicro 2015. Published. 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro 2015), Salvador.
Assalti, R., Pavanello, M. A., Flandre, D., & de Souza, M. (2015). Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications. Proceedings of SBMicro 2015. Published. 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro 2015), Salvador. https://doi.org/10.1109/SBMicro.2015.7298120
Francis, L., André, N., Gérard, P., Zeeshan Ali, S., Udrea, F., & Flandre, D. (2015). A Low-Power and In Situ Annealing Mitigation Technique for Fast Neutrons Irradiation of Integrated Temperature Sensing Diodes. Proceedings of ANIMMA 2015. Published. Advancements in Nuclear Instrumentation, Measurement Methods and Their Applications (ANIMMA 2015), Lisbon (Portugal). https://doi.org/10.1109/ANIMMA.2015.7465594
André, N., Li, G., Gérard, P., Poncelet, O., Zeng, Y., Ali, S. Z., Udrea, F., Francis, L., & Flandre, D. (2015). Wide Band Study of Silicon-on-Insulator Photodiodes on suspended Micro-hotplates Platforms. Proceedings of ICICDT 2015, 1-4. https://doi.org/10.1109/ICICDT.2015.7165879
Article de journal
Proost, J., Deschuyteneer, G., Santoro, R., Van Overmeere, Q., Soumillion, P., & Flandre, D. (2015). Filamentous Phages Displaying Multivalent Peptide Motives With Specific Affinity To Anodic Alumina Surfaces. Journal of Biosensors & Bioelectronics, 6(1), 1000162. https://doi.org/10.4172/2155-6210.1000162 (Original work published 2015)
Kotipalli, R. V. R., Vermang, B., Joel, J., Jaiswar, R. R., Edoff, M., & Flandre, D. (2015). Investigating the electronic properties of Al2O3/Cu(In, Ga)Se2 interface. A I P Advances, 5(107101), 6. https://doi.org/10.1063/1.4932512 (Original work published 2015)
N. de S. Fino, L., A. G. Silveira, M., Renaux, C., Flandre, D., & Pinillos Gimenez, S. (2015). The Influence of Back Gate Bias on the OCTO SOI MOSFET’s Response to X-ray Radiation. Journal of Integrated Circuits and Systems, 10(1), 43-48. (Original work published 2015)
El Hamid, H. A., Iniguez, B., Kilchytska, V., Flandre, D., & Ismail, Y. (2015). An analytical 3D model for short-channel effects in undoped FinFETs. Journal of Computational Electronics, 14(2), 500-505. https://doi.org/10.1007/s10825-015-0678-0 (Original work published 2015)
Kilchytska, V., Makovejev, S., Barraud, S., Poiroux, T., Raskin, J.-P., & Flandre, D. (2015). Trigate nanowire MOSFETs analog figures of merit. Solid-State Electronics, 112, 78-84. https://doi.org/10.1016/j.sse.2015.02.003 (Original work published 2015)
Al Kadi Jazairli, M., & Flandre, D. (2015). A 65 nm CMOS Ultra-Low-Power Impulse Radio-Ultra-Wideband Emitter for Short-Range Indoor Localization. Journal of Low Power Electronics, 11(3), 349-358. https://doi.org/10.1166/jolpe.2015.1393 (Original work published 2015)
Rasson, J., Couniot, N., Van Overstraeten, N., Jacques, L., Francis, L., & Flandre, D. (2015). Quantitative characterization of biofunctionalization layers by robust image analysis for biosensor applications. Sensors and Actuators B: Chemical : international journal devoted to research and development of physical and chemical transducers, 222, 980-986. https://doi.org/10.1016/j.snb.2015.09.028 (Original work published 2016)
Couniot, N., Francis, L., & Flandre, D. (2015). Resonant dielectrophoresis and electrohydrodynamics for high-sensitivity impedance detection of whole-cell bacteria. Lab On a Chip : miniaturisation for chemistry, physics, biology and bioengineering, 15, 3183-3191. https://doi.org/10.1039/c5lc00090d (Original work published 2015)
Couniot, N., Afzalian, A., Van Overstraeten, N., Francis, L., & Flandre, D. (2015). Capacitive biosensing of bacterial cells: Analytical model and numerical simulations. Sensors and Actuators B: Chemical : international journal devoted to research and development of physical and chemical transducers, 211, 428-438. https://doi.org/10.1016/j.snb.2015.01.108 (Original work published 2015)
Novo, C., Baptista, J., Guazzeli da Silveira, M., Giacomini, R., Afzalian, A., & Flandre, D. (2015). Study of Total Quantum Efficiency of Lateral SOI PIN Photodiodes with Back-Gate Bias, Intrinsic Length and Temperature Variation. ECS transactions, 66(5), 101-107. https://doi.org/10.1149/06605.0101ecst (Original work published 2015)
Kotipalli, R. V. R., Vermang, B., Fjällström, V., Edoff, M., Delamare, R., & Flandre, D. (2015). Influence of Ga/(Ga + In) grading on deep-defect states of Cu(In,Ga)Se2 solar cells. Physica Status Solidi. Rapid Research Letters, 4. https://doi.org/10.1002/pssr.201510024 (Original work published 2015)
Kazemi Esfeh, B., Kilchytska, V., Barral, V., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2015). Assessment of 28nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements. Solid-State Electronics, 117, 130-137. https://doi.org/10.1016/j.sse.2015.11.020 (Original work published 2015)
Rudenko, T., Nazarov, A., Kilchytska, V., & Flandre, D. (2015). A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling. Solid-State Electronics, 117, 66-76. https://doi.org/10.1016/j.sse.2015.11.017 (Original work published 2015)
Navarenho de Souza Fino, L., Davini Neto, E., Aparecida Guazzelli da Silveira, M., Renaux, C., Flandre, D., & Pinillos Gimenez, S. (2015). Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET. Semiconductor Science and Technology, 30(105024), 12. https://doi.org/10.1088/0268-1242/30/10/105024 (Original work published 2015)
Couniot, N., de Streel, G., Botman, F., Kuti Lusala, A., Flandre, D., & Bol, D. (2015). A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. IEEE Journal of Solid State Circuits, 50(10), 2419-2430. https://doi.org/10.1109/JSSC.2015.2457897 (Original work published 2015)
Makovejev, S., Planes, N., Haond, M., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2015). Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI. Solid-State Electronics, 115, 219-224. https://doi.org/10.1016/j.sse.2015.08.022 (Original work published 2015)
de Souza, M., Flandre, D., Trevisoli Doria, R., Trevisoli, R., & Pavanello, M. A. (2015). On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration. Solid-State Electronics, 117, 152-160. https://doi.org/10.1016/j.sse.2015.11.018 (Original work published 2015)
Makovejev, S., Kazemi Esfeh, B., Barral, V., Planes, N., Haond, M., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2015). Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications. Solid-State Electronics, 6. https://doi.org/10.1016/j.sse.2014.12.007 (Original work published 2015)
Gimenez, S. P., Galembeck, E. H. S., Renaux, C., & Flandre, D. (2015). Diamond layout style impact on SOI MOSFET in high temperature environment. Microelectronics Reliability, MR_11492, 6. https://doi.org/10.1016/j.microrel.2015.02.015 (Original work published 2015)
Couniot, N., Francis, L., & Flandre, D. (2015). A 16 x 16 CMOS Capacitive Biosensor Array Towards Detection of Single Bacterial Cell. IEEE Transactions on Biomedical Circuits and Systems. Accepted/in-press. https://doi.org/10.1109/TBCAS.2015.2416372 (Original work published 2015)
Couniot, N., Bol, D., Poncelet, O., Francis, L., & Flandre, D. (2015). A Capacitance-to-Frequency Converter with On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers up to 575 MHz. IEEE Transactions on Circuits and Systems. Part 2: Express Briefs, 62(2), 159-163. https://doi.org/10.1109/TCSII.2014.2369111 (Original work published 2015)
Article de journal
De Vos, J., Flandre, D., & Bol, D. (2014). A Sizing Methodology for On-Chip switched-Capacitor DC/DC Converters. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 61(5), 15971606. https://doi.org/10.1109/TCSI.2013.2285692 (Original work published 2014)
Gimenez, S. P., Davini, E., Peruzzi, V., Renaux, C., & Flandre, D. (2014). Compact diamond MOSFET model accounting for PAMDLE applicable down 150nm node. Electronics Letters, 50(22), 1618-1620. https://doi.org/10.1049/el.2014.1229 (Original work published 2014)
Novo, C., Giacomini, R., Doria, R., Afzalian, A., & Flandre, D. (2014). Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures. Semiconductor Science and Technology, 29(075008), 9. https://doi.org/10.1088/0268-1242/29/7/075008 (Original work published 2014)
Md Arshad, M. K., Kilchytska, V., Emam, M., Andrieu, F., Flandre, D., & Raskin, J.-P. (2014). Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit. Solid-State Electronics, 97, 38-44. https://doi.org/10.1016/j.sse.2014.04.027 (Original work published 2014)
Rudenko, T., Md Arshad, Raskin, J.-P., Nazarov, A., Flandre, D., & Kilchytska, V. (2014). On the gm/ID-based approaches for threshold voltage extraction in advanced MOSFETs and their application to ultra-thin body SOI MOSFETs. Solid-State Electronics, 97, 52-58. https://doi.org/10.1016/j.sse.2014.04.029 (Original work published 2014)
Vermang, B., Wätjen, J. T., Fjällström, V., Rostvall, F., Edoff, M., Kotipalli, R. V. R., Henry, F., & Flandre, D. (2014). Employing Si solar cell technology to increase efficiency of ultra-thin Cu(In,Ga)Se2 solar cells. Progress in Photovoltaics : research and applications, 7. https://doi.org/10.1002/pip.2527 (Original work published 2014)
Dutu, C. A., Vlad, A., Reckinger, N., Flandre, D., Raskin, J.-P., & Melinte, S. (2014). Tuning the surface conditioning of trapezoidally shaped silicon nanowires by (3-aminopropyl)triethoxysilane. Applied Physics Letters, 104(2), 023502 (4). https://doi.org/10.1063/1.4861598 (Original work published 2014)
Couniot, N., Vanzieleghem, T., Rasson, J., Van Overstraeten, N., Poncelet, O., Mahillon, J., Francis, L., & Flandre, D. (2014). Lytic enzymes as selectivity means for label-free, microfluidic and impedimetric detection of whole-cell bacteria using ALD-Al2O3 passivated microelectrodes. Biosensors and Bioelectronics, 67, 154-161. https://doi.org/10.1016/j.bios.2014.07.084 (Original work published 2014)
Druart, S., Flandre, D., & Francis, L. (2014). A Self-Oscillating System to Measure the Conductivity and the Permittivity of Liquids within a Single Triangular Signal. Journal of Sensors, 2014(389764), 11. https://doi.org/10.1155/2014/389764 (Original work published 2014)
Garduno, S. I., Alvarado Pulido, J. J., Cerdeira, A., Estrada, M., Kilchytska, V., & Flandre, D. (2014). Gate leakage currents model for FinFETs implemented in Verilog-A for electronic circuits design. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 15. https://doi.org/10.1002/jnm.1988 (Original work published 2014)
Makovejev, S., Kazemi Esfeh, B., Andrieu, F., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2014). Assessment of Global Variability in UTBB MOSFETs in Subthreshold Regime. Journal of Low Power Electronics and Applications, 4(3), 201-213. https://doi.org/10.3390/jlpea4030201 (Original work published 2014)
Vermang, B., Wätjen, J. T., Fjällström, V., Rostvall, F., Edoff, M., Gunnarsson, R., Pilch, I., Helmersson, U., Kotipalli, R. V. R., Henry, F., & Flandre, D. (2014). Highly Reflective Rear Surface Passivation Design For Ultra-Thin Cu(In,Ga)Se² Solar Cells. Thin Solid Films, 582, 300-303. https://doi.org/10.1016/j.tsf.2014.10.050 (Original work published 2014)
Kamel, D., Renauld, M., Flandre, D., & Standaert, F.-X. (2014). Understanding the limitations and improving the relevance of SPICE simulations in side-channel security evaluations. Journal of Cryptographic Engineering, 4, 1987-1995. https://doi.org/10.1007/S13389-014-0080-z (Original work published 2014)
Van Overstraeten, N., Lefèvre, O., Couniot, N., & Flandre, D. (2014). Assessment of different functionalization methods for grafting a protein to an alumina-covered biosensor. Biofabrication, 6(3), 35007. https://doi.org/10.1088/1758-5082/6/3/035007 (Original work published 2014)
Descamps, P., Asad, S. S., Kaiser, V., Campeol, F., Kuzma-Filipek, I., Duerinckx, F., Szlufcik, J., Flandre, D., Kotipalli, R. V. R., Delamare, R., & Beaucarne, G. (2014). Deposition of a SiOx Film Showing Enhanced Surface Passivation. Energy Procedia, 55, 769-776. https://doi.org/10.1016/j.egypro.2014.08.058 (Original work published 2014)
Kilchytska, V., Alvarado Pulido, J. J., Collaert, N., Rooyakers, R., Militaru, O., Berger, G., & Flandre, D. (2014). Total-Dose Effects Caused by High-Energy Neutrons and y-Rays in Multiple-Gate FETs. IEEE Transactions on Nuclear Science, 57(4), 1764-1770. (Original work published 2010)
André, N., Rue, B., Scheen, G., Flandre, D., Francis, L., & Raskin, J.-P. (2014). Out-of-plane MEMS-based mechanical airflow sensor co-integrated in SOI CMOS technology. Sensors and Actuators A: Physical : an international journal devoted to research and development of physical and chemical transducers, 206, 67-74. https://doi.org/10.1016/j.sna.2013.11.017 (Original work published 2013)
Papier de conférence
Assalti, R., Pavanello, M. A., Flandre, D., & de Souza, M. (2014). Dependence of the Optimum Length of Lightly Doped Region of GC SOI nMOSFET with Front Gate Bias. 29th Symposium on Microelectronics Technology and Devices (SBMicro 2014), Aracaju (Brazil).
Trevisoli, R., de Souza, M., Doria, R. D., Kilchytska, V., Flandre, D., & Pavanello, M. A. (2014). Effect of the Temperature on Junctionless Nanowire Transistors Electrical Parameters down to 4K. 29th Symposium on Microelectronics Technology and Devices (SBMicro 2014), Aracaju (Brazil). https://doi.org/10.1109/SBMicro.2014.6940134
Flandre, D., Kilchytska, V., Boufouss, E. H., & Alvarado Pulido, J. J. (2014). Analog design in SOI for hostile environments and high temperatures. EAMTA/CAMTA 2014, Mendoza (Argentina).
d’Oliveira, L. M., Flandre, D., Pavanello, M. A., & de Souza, M. (2014). Effect of High Temperature on Analog Parameters of Asymmetric Self-Cascode SOI nMOSFETs. 29th Symposium on Microelectronics Technology and Devices (SBMicro 2014), Aracaju (Brazil).
Flandre, D. (2014). A talk about university – industry R&D collaborations in the contexts of Walloon competitiveness clustersand European projects on topics such as microsystems for aerospace or biomedical applications. EAMTA/CAMTA 2014, Mendoza (Argentina).
de Streel, G., De Vos, J., Flandre, D., & Bol, D. (2014). A 65nm 1V to 0.5V Linear Regulator with Ultra Low Quiescent Current for Mixed-Signal ULV SoCs. 2014 IEEE FTFC Conference, Monaco. https://doi.org/10.1109/FTFC.2014.6828597
Assalti, R., Pavanello, M. A., de Souza, M., & Flandre, D. (2014). Technological Parameters Scaling Influence on the Analog Performance of Graded-Channel SOI nMOSFET Transistors. International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Playa del Carmen (Mexico). https://doi.org/10.1109/ICCDCS.2014.7016159
Makovejev, S., Kazemi Esfeh, B., Barral, V., Planes, N., Haond, M., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2014). Wide Frequency Band Assessment of 28 nm FDSOI Technology Platform for Analogue and RF Applications. Proceedings of the 15th International Conference on ULTIMATE INTEGRATION ON SILICON (ULIS 2014), p. 2.
Haddad, P.-A., Gosset, G., Raskin, J.-P., & Flandre, D. (2014). Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current. 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). Published. SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE, Millbrae, CA, USA. https://doi.org/10.1109/S3S.2014.7028220
De Vos, J., Flandre, D., & Bol, D. (2014). Switched-Capacitor DC/DC Converters for Empowering Internet-of-Things SoCs. 2014 IEEE FTFC Conference, Monaco. https://doi.org/10.1109/FTFC.2014.6828615
Kilchytska, V., Makovejev, S., Barraud, S., Poiroux, T., Raskin, J.-P., & Flandre, D. (2014). Trigate NanoWire MOSFETs Analog Figures of Merit. Proceedings of the 10th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2014), p. 2.
Flandre, D. (2014). Advanced SOI Performances & Ultra-Low-Power Design Examples. EAMTA/CAMTA 2014, Mendoza (Argentina).
Flandre, D. (2014). Advanced CMOS SOI Technologies & designs for high operational temperature micro-systems. IMAPS-Benelux Winter Event 2014 - Heat management in Microelectronic systems, Gent (Belgium).
d’Oliveira, L. M., Trevisoli, D., Pavanello, M. A., de Souza, M., Kilchytska, V., & Flandre, D. (2014). Asymmetric self-cascode FD SOI nMOSFETs harmonic distortion at cryogenic temperatures. 11th International Workshop on Low Temperature Electronics (WOLTE 2014), Grenoble (France). https://doi.org/10.1109/WOLTE.2014.6881025
Makovejev, S., Barraud, S., Poiroux, T., Rozeau, O., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2014). Impact of Self-Heating on UTB MOSFET Parameters. Proceedings of the 10th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2014). Published. 10th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2014), Tarragona (Spain).
André, N., Pollissard, G., Couniot, N., Gérard, P., Ali, Z. S., Udrea, F., Francis, L., & Flandre, D. (2014). A silicon-on-insulator (SOI) platform functionalized by atomic layer deposition (ALD) for humidity sensing. International Meeting on New Sensing Technologies and Modelling for Air-Pollution Monitoring, Aveiro (Portugal).
Olbrechts, B., & Rue, B. (2014). PMOSFET-based Pressure Sensors in FD SOI.
de Souza Fino, L. N., Aparecida Guazzelli da Silveira, M., Renaux, C., Flandre, D., & Pinillos Gimenez, S. (2014). Boosting the Radiation Hardness and Higher Reestablishing Pre-Rad Conditions by Using OCTO Layout Style for MOSFETs. Proceedings of SBMicro 2014, 1-8. https://doi.org/10.1109/SBMicro.2014.6940133
Flandre, D. (2014). SOI CMOS sensors, transistors and circuits for ultra-low-power and harsh environment applications. The 10th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits, Tarragona (Spain).
Kilchytska, V., Makovejev, S., Raskin, J.-P., & Flandre, D. (2014). Advantages and Challenges of Advanced MOSFETs for Analog and RF Applications. Abstratcs - CMOS Emerging Technologies Research Symposium, p. 33.
Kazemi Esfeh, B., Kilchytska, V., Barral, V., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2014). 28 nm FD SOI Technology Platform RF FoM. Proceedings of the 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference. Published. 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2014), Millbrae (USA). https://doi.org/10.1109/S3S.2014.7028208
Trevisoli, R., de Souza, M., Doria, R. T., Kilchytska, V., Flandre, D., & Pavanello, M. A. (2014). Analog operation of Junctionless Nanowire Transistors down to liquid helium temperature. 11th International Workshop on Low Temperature Electronics (WOLTE 2014), Grenoble (France). https://doi.org/10.1109/WOLTE.2014.6881024
Olbrechts, B., & Rue, B. (2014). MOSFETs-based Pressure Sensors in Thin Film SOI Technology.
Martins d’Oliveira, L., Trevisoli Doria, R., Pavanello, M. A., de Souza, M., & Flandre, D. (2014). Analysis of Harmonic Distortion of Asymmetric Self-Cascode Association of SOI nMOSFETs Operating in Saturation. International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Playa del Carmen (Mexico). https://doi.org/10.1109/ICCDCS.2014.7016161
Flandre, D. (2014). A talk about university - industry relationships, transfers and start-up creation. Innovation & Entrepreneurship in CAS, ISEP, Issy-Les-Moulineaux (France).
Flandre, D., & Bol, D. (2014). Designing robust subthreshold and ultra-low-voltage mixed-signal circuits against progress variations, temperature and radiation effects. 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2014), San Francisco (USA).
De Vos, J., Kilchytska, V., Flandre, D., & Bol, D. (2014). Compensation of Total Ionizing Dose Effects in ULV SoCs Through Adaptive Voltage Scaling. 2014 IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco (USA). https://doi.org/10.1109/S3S.2014.7028238
Makovejev, S., Kazemi Esfeh, B., Raskin, J.-P., Kilchytska, V., Flandre, D., Barral, V., Planes, N., & Haond, M. (2014). Variability of UTBB MOSFET Analog Figures of Merit in Wide Frequency Range. Proceedings of the 2014 4th European Solid State Device research Conference (ESSDERC 2014), 222-225. https://doi.org/10.1109/ESSDERC.2014.6948800
Francis, L., Druart, S., & Flandre, D. (2014). A Self-Oscillating System to Characterize Liquid Salinities within a Single triangular Waveform Signal. 20th IMEKO TC4 International Symposium and 18th International Workshop on ADC Modelling and Testing - Research on Electric and Electronic Measurement for the Economic Upturn, Benevento (Italy).
André, N., Pollissard, G., Couniot, N., Gérard, P., Ali, Z., Udrea, F., Francis, L., & Flandre, D. (2014). Harsh Environment Water Vapour Sensing Platforms in SOI Technology. CMOS Emerging Technologies Research Symposium, Grenoble (France).
Couniot, N., Vanzieleghem, T., Rasson, J., Van Overstraeten, N., Poncelet, O., Mahillon, J., Francis, L., & Flandre, D. (2014). Impedance spectroscopy using lysin as selectivity means for detection of bacteria. Winfab Day 2014, Louvain-La-Neuve.
Francis, L., André, N., Boufouss, E. H., Gérard, P., Ali, Z., Udrea, F., & Flandre, D. (2014). The effects of gamma irradiation on micro-hotplates with integrated temperature sensing diodes. SPIE - The International Society for Optical Engineering, Baltimore (USA). https://doi.org/10.1117/12.2050734
Chapitre de livre
Wang, W., Rohan, J. F., Wang, N., Hayes, M., Romani, A., Macrelli, E., Dini, M., Filippi, M., Tartagni, M., & Flandre, D. (2014). Smart Energy Management and Conversion. In Francis Balestra (ed.), Beyond-CMOS Nanodevices 1 (p. p. 249-271). John Wiley & Sons, Inc. https://doi.org/10.1002/9781118984772.ch9
Kilchytska, V., Makovejev, S., Md Arshad, M. K., Raskin, J.-P., & Flandre, D. (2014). Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications. In Alexei Nazarov, Francis Balestra, Valeriya Kilchytska, Denis Flandre (ed.), Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting (p. p. 27-46). Springer International Publishing. https://doi.org/10.1007/978-3-319-08804-4_2
Palestri, P., Mouis, M., Afzalian, A., Selmi, L., Pittino, F., Flandre, D., & Ghibaudo, G. (2014). Sensitivity of Silicon Nanowire Biochemical Sensors. In Francis Balestra (ed.), Beyond-CMOS Nanodevices 1 (p. p. 43-63). John Wiley & Sons, Inc. https://doi.org/10.1002/9781118984772.ch3
Monographie
Nazarov, A., Balestra, F., Kilchytska, V., & Flandre, D. (2014). Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting. Springer International Publishing.
Nazarov, A. N., Lysenko, V. S., & Flandre, D. (2014). Functional Nanomaterials and Devices VII. Trans Tech Publications Ltd.
Article de journal
Rudenko, T., Nazarov, A., Kilchytska, V., Flandre, D., Popov, V., Ilnitsky, M., & Lysenko, V. (2013). Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs. Fizika Napivprovidnikiv Kvantova ta Optoelektronika, 16(3), 300-309. (Original work published 2013)
Garduῆo, S. I., Cerdeira, A., Estrada, M., Alvarado Pulido, J. J., Kilchytska, V., & Flandre, D. (2013). Improved modeling of gate leakage currents for fin-shaped field-effect transistors. Journal of Applied Physics, 113(124507), 124507. https://doi.org/10.1063/1.4795403 (Original work published 2013)
Pollissard, G., Gosset, G., & Flandre, D. (2013). A modified gm/ID design methodology for deeply scaled CMOS technologies. Analog Integrated Circuits and Signal Processing, 78(3), 771-784. https://doi.org/10.1007/s10470-013-0166-z (Original work published 2013)
Md Arshad, M. K., Makovejev, S., Olsen, S. H., Andrieu, F., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2013). UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetic double-gate regime. Solid-State Electronics, 90, 56-64. (Original work published 2013)
Bouterfa, M., Alexandre, G., Cortina Gil, E., & Flandre, D. (2013). Charge collection mapping of a novel ultra-thin silicon strip detector for hardrontherapy beam monitoring. Nuclear Instruments & Methods in Physics Research. Section A: Accelerators, Spectrometers, Detectors, and Associated Equipment, 732, 556-559. https://doi.org/10.1016/j.nima.2013.05.139 (Original work published 2013)
Cerdeira, A., Estrada, M., Alvarado Pulido, J. J., Garduno, I., Contreras, E., Tinoco, J., Iniguez, B., Kilchytska, V., & Flandre, D. (2013). Review on double-gate MOSFETs and FinFETs modeling. Facta Universitatis. Series Electronics and Energetics, 26(3), 197-213. https://doi.org/10.2298/FUEE1303197C (Original work published 2013)
Druart, S., Gillis, J. M., Martin, J. M., Flandre, D., & Francis, L. (2013). Detector of abrupt current variations on power lines. Electronics Letters, 49(14), 886-887. https://doi.org/10.1049/el.2013.1334 (Original work published 2013)
Couniot, N., Flandre, D., Francis, L., & Afzalian, A. (2013). Signal-to-noise ratio optimization for detecting bacteria with interdigitated microelectrodes. Sensors and Actuators B: Chemical : international journal devoted to research and development of physical and chemical transducers, 9 pages. https://doi.org/10.1016/j.snb.2012.12.008 (Original work published 2013)
Kotipalli, R. V. R., Delamare, R., Poncelet, O., Tang, X., Francis, L., & Flandre, D. (2013). Passivation effects of atomic-layer-deposited aluminium oxide. EPJ Photovoltaics, 4(45107), 1-8. https://doi.org/10.1051/epjpv/2013023 (Original work published 2013)
Kilchytska, V., Bol, D., De Vos, J., Andrieu, F., & Flandre, D. (2013). Quasi-Double Gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications. Solid-State Electronics, 84, 28-37. https://doi.org/10.1016/j.sse.2013.02.018 (Original work published 2013)
Bouterfa, M., & Flandre, D. (2013). Validation of a Novel ultra-thin silicon Strip Detector for Hadron Therapy beam monitoring. Journal of Circuits Systems and Computers, 22(9), 6. https://doi.org/10.1142/s0218126613400185 (Original work published 2013)
de Souza, M., Cardoso Paz, B., Flandre, D., & Pavanello, M. A. (2013). Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs. Microelectronics Reliability, 848-855. https://doi.org/10.1016/j.microrel.2013.03.005 (Original work published 2013)
Nemer, J. P., de Souza, M., Flandre, D., & Pavanello, M. A. (2013). Analog Behavior of Submicron Graded-Channel SOI MOSFETs Varying the Channel Length, Doping Concentration and Temperature. ECS Transactions, 53(5), 149-154. https://doi.org/10.1149/05305.0149ecst (Original work published 2013)
Bol, D., De Vos, J., Hocquet, C., Botman, F., Boyd, S. P., Flandre, D., & Legat, J.-D. (2013). SleepWalker: a 25-MHz 0.4-V sub-mm² 7-µW/MHz microcontroller in 65-nm LP/GP CMOS for low-carbon wireless sensor nodes. IEEE Journal of Solid State Circuits, vol. 48(no. 1), pp 20-32. https://doi.org/10.1109/JSSC.2012.2218067 (Original work published 2013)
Gimenez, S. P., Leoni, R. D., Renaux, C., & Flandre, D. (2013). Using diamond layout style to boost MOSFET frequency response of analogue IC. Electronics Letters, ELL-2013-4038.R2(50-5), 398-400. https://doi.org/10.1049/el.2013.4038 (Original work published 2013)
Md Arshad, Makovejev, S., Olsen, S., Andrieu, F., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2013). UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime. Solid-State Electronics. Published. https://doi.org/10.1016/j.sse.2013.02.051 (Original work published 2013)
Boufouss, E. H., Francis, L., Kilchytska, V., Gérard, P., Simon, P., & Flandre, D. (2013). Ultra-low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference. Sensors, 13(12), 17265-17280. https://doi.org/10.3390/s131217265 (Original work published 2013)
Tang, X., Francis, L., Gong, L., Wang, F., Raskin, J.-P., Flandre, D., Zhang, S., You, D., Wu, L., & Dai, B. (2013). Characterization of high-efficiency multi-crystalline silicon in industrial production. Solar Energy Materials & Solar Cells, 117, 225-230. https://doi.org/10.1016/j.solmat.20313.06.013 (Original work published 2013)
Papier de conférence
Afzalian, A., & Flandre, D. (2013). Advanced Nanoscale FET Biosensors: Route Towards Single Analyte Detection. Proceedings of the 2013 CMOS Emerging Technology Research Symposium. Published. CMOS Emerging Technology Research Symposium, Whistler (BC Canada).
Bol, D., De Vos, J., Botman, F., de Streel, G., Bernard, S., Flandre, D., & Legat, J.-D. (2013). Green SoCs for a sustainable Internet-of-Things. Faible Tension Faible Consommation (FTFC), 2013 IEEE, p. 4 pages. https://doi.org/10.1109/FTFC.2013.6577767
Afzalian, A., & Flandre, D. (2013). NEGF Computational study if Advanced Nanoscale FET Biosensors for Single DNA Molecule Detection. Proceedings of the 2013 Silicon Nanoelectronics Workshop, 2.
Kotipalli, R. V. R., Delamare, R., Henry, F., Proost, J., & Flandre, D. (2013). Thermal stability analysis of DC-sputtered AL2O3 films for surface passivation of C-Si solar cells. Proceedings of the 28th European Photovoltaic Solar Energy Conference and exhibition (EU PVSEC 2013), 4.
Kilchytska, V., Makovejev, S., Md Arshad, M. K., Raskin, J.-P., Flandre, D., Andrieu, F., Poiroux, T., & Faynot, O. (2013). Perspectives of UTBB FD SOI MOSFETs for analog and RF applications. Proceedings of the 2nd Ukrainian-French Seminar “Semiconductor on Insulator Materials, Devices and Circuits: Physics, Technology and Diagnostics, and 7th International Workshop “Functional Nanomaterials and Devices”. Published. 2nd Ukrainian-French Seminar : Semiconductor on Insulator Materials, Devices and Circuits: Physics, Technology and Diagnostics, and 7th International Workshop : Functional Nanomaterials and Devices, Kyiv (Ukraine).
de Souza, M., Flandre, D., & Pavanello, M. A. (2013). Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. 2013 Symposium on Microelectronics Technology and Devices (SBMicro), Curutiba (Brazil). https://doi.org/10.1109/SBMicro.2013.6676154
Nemer, J. P., de Souza, M., Flandre, D., & Pavanello, M. A. (2013). Low frequency noise in submicron Graded-Channel SOI MOSFETs. 2013 Symposium on Microelectronics Technology and Devices (SBMicro), Curutiba (Brazil). https://doi.org/10.1109/SBMicro.2013.6676173
Bouterfa, M., Aouadi, K., Flandre, D., & Cortina Gil, E. (2013). Characterization of Ultra-Thin Silicon Strip Detectors for Hardontherapy Beam Monitoring. Proceedings of the IEEE Instrumentation and Measurement Technology Conference 2013 (I2MTC 2013), p. 1088-1091.
Makovejev, S., Kazemi Esfeh, B., Andrieu, F., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2013). Threshold Voltage Extraction Techniques and Temperature Effect in Context of Global Variability in UTBB MOSFETs. Proceedings of the 43rd European Solid-State Device Research Conference (ESSDERC 2013), 4. https://doi.org/10.1109/ESSDERC.2013.6818852
Novo, C., Giacomini, R., Doria, R., Afzalian, A., & Flandre, D. (2013). Back-gate Bias Influence on the Operation of Lateral SOI PIN Photodiodes at High Temperatures. Proceedings of the 2013 EUROSOI Conference, p. 2 pages.
Francis, L., Gkotsis, P., Kilchytska, V., Tang, X., Druart, S., Raskin, J.-P., & Flandre, D. (2013). Impact of radiations on the electromechanical properties of materials and on the piezoresistive and capacitive transduction mechanisms used in microsystems. Proceedings of SPIE 8614. Published. Reliability, Packaging, Testing, and Characterization of MOEMS/MEMS and Nanodevices XII (SPIE 2013), San Francisco (USA). https://doi.org/10.1117/12.2008531
Navarenho de Souza Fino, L., Guazzelli da Silveira, M. A., Renaux, C., Flandre, D., & Gimenez, S. P. (2013). Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style. Proceedings of SBMicro 2013, 1-4. https://doi.org/10.1109/SBMicro.2013.6676166
Al Kadi Jazairli, M., & Flandre, D. (2013). An Ultra-Low-Power UWB IR pulse receiver using 65nm CMOS technology. Proceedings de 2013 IEEE Faible Tension Faible Consommation (FTFC 2013), p. 1-4. https://doi.org/10.1109/FTFC.2013.6577758
Md Arshad, M. K., Kilchytska, V., Emam, M., Andrieu, F., Flandre, D., & Raskin, J.-P. (2013). Effect of parasitic elements on UTBB FD SOI MOSFET RF figures of merit. Proceedings of the Ninth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2012), p. 2.
Novo, C., Giacomini, R., Afzalian, A., & Flandre, D. (2013). Operation of Lateral SOI Pin Photodiodes with Back-Gate Bias and Intrinsic Length Variation. Transactions of 223rd ECS Meeting. Published. 223rd ECS Meeting, Toronto (Canada).
de Souza Fino, L. N., Aparecida Guazzelli da Silveira, M., Renaux, C., Flandre, D., & Gimenez, S. P. (2013). Comparative Experimental Study of X-Ray Radiation Effects in the Threshold Voltage between the OCTO and Conventional SOI nMOSFETs. VIII Workshop on Semiconductors and Micro & Nano Technology (Seminatec 2013), Campinas (Brazil).
Melinte, S., Iordanescu, A.-G., Dutu, C. A., Flandre, D., Faniel, S., Rodrigues Martins, F., & Hackens, B. (2013). Fabrication, electrical characterization and scanning gate microscopy of Schottky silicon nanowire devices. Bulletin of the American Physical Society, 1.
Afzalian, A., Lherbier, A., Charlier, J.-C., & Flandre, D. (2013). Multiscale Simulation of Epoxide Adsorbate Functionalization on Graphene Nanoribbons. Proceedings of the 16th International Workshop on Computational Electronics, p. 40-41.
Rudenko, T., Md Arshad, M. K., Raskin, J.-P., Nazarov, A., Flandre, D., & Kilchytska, V. (2013). On the gm/ID-based Threshold Voltage Extractions in Advanced SOI MOSFETs. Proceedings of the Ninth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2013), p. 2.
Makovejev, S., Kazemi Esfeh, B., Andrieu, F., Raskin, J.-P., Flandre, D., & Kilchytska, V. (2013). Global Variability of UTBB MOSFET in Subthreshold. Proceedings of the IEEE S3S Conference 2013, 2. https://doi.org/10.1109/S3S.2013.6716585
de Souza Fino, L. N., Aparecida Guazzelli da Silveira, M., Renaux, C., Flandre, D., & Pinillos Gimenez, S. (2013). Total Ionizing Dose Effects on the Digital performance of Irradiated OCTO and Conventional Fully Depleted SOI MOSFET. 14th European Conference on radiation and its Effects on Components and Systems (RADECS 2013), Oxford (UK).
Boufouss, E. H., Gérard, P., Simon, P., Francis, L., & Flandre, D. (2013). High Temperature and Radiation Hard CMOS SOI Sub-threshold Voltage Reference. Proceedings of the IEEE S3S Conference 2013, 2. https://doi.org/10.1109/S3S.2013.6716543
Brevet
Bawedin, M., Cristoloveanu, S. I., Flandre, D., Renaux, C., & Crahay, A. (2013). Double-gate floating-body memory device (Patent No. WO2009/087125).
Chapitre de livre
Kilchytska, V., Raskin, J.-P., & Flandre, D. (2013). Specific Features of MuGFETs at High Temperatures over a Wide Frequency Range. In Nadine Collaert (ed.), CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications (pp. 233-259). Pan Stanford Publishing Pte Ltd. https://doi.org/10.1201/b13063-9
Balestra, F., & Flandre, D. (2013). Introduction to part 3, in Nanoscale CMOS. In Balestra, Francis (éd.) (ed.), Nanoscale CMOS. Innovative Materials, Modeling and Characterization (p. p. 471-474). John Wiley & Sons, Inc. https://doi.org/10.1002/9781118621523.ch13
Chapitre de livre
Afzalian, A., & Flandre, D. (2012). Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-stage Transimpedance Amflifiers in Thin-Film SOI CMOS Technology. In Ilgu Yun (ed.), Photodiodes - From Fundamentals to Applications (p. p. 331-368). InTech. https://doi.org/10.5772/50531
Dupuis, P., Van Overstraeten, N., Raskin, J.-P., Francis, L., & Flandre, D. (2012). Some mitigations for unequal data variance in linear regression. In Advanced Mathematical and Computational Tools in Metrology and Testing IX (p. pp. 118-125). World Scientific Publishing Vompany. https://doi.org/10.1142/9789814397957_0015
Papier de conférence
Rudenko, T., Nazarov, A., Kilchytska, V., & Flandre, D. (2012). Threshold voltage of advanced MOSFETs: Physical criteria and experimental extraction methods. Book of Abstracts of the International Conference “Micro- and Nanoelectronics-2012” (ICMNE-2012), 1.
Alvarado, J., Tinoco, J. C., Kilchytska, V., Flandre, D., Raskin, J.-P., Cerdeira, A., & Contreras, E. (2012). Compact small-signal model for RF FinFETs. Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), 1-4. https://doi.org/10.1109/ICCDCS.2012.6188936
Kilchytska, V., Andrieu, F., & Flandre, D. (2012). On the UTBB SOI MOSFET Performance Improvement in Quasi-Double-Gate Regime. Proceedings of the 2012 European Solid-State Device Research Conference (ESSDERC 2012), 246-249. https://doi.org/10.1109/ESSDERC.2012.6343379
Afzalian, A., Couniot, N., & Flandre, D. (2012). Detection Limit of ultra-scaled Nanowire Biosensors. Proceedings of the 2012 SISPAD Conference, 165-168.
Md Arshad, M. K., Kilchytska, V., Makovejev, S., Olsen, S. H., Andrieu, F., Raskin, J.-P., & Flandre, D. (2012). UTBB SOI MOSFETs analog figures of merit: effect of ground plane and asymmetric double-gate regime. Proceedings of the Eighth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits – EuroSOI’12, 111-112.
Flandre, D., Bulteel, O., Gosset, G., Rue, B., & Bol, D. (2012). Ultra-low-power analog and digital circuits and microsystems using disruptive ultra-low-leakage design techniques. Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), 1-2. https://doi.org/10.1109/ICCDCS.2012.6188884
Rudenko, T., Nazarov, A., Kilchytska, V., & Flandre, D. (2012). Revision of interface coupling in ultra-thin body SOI MOSFETs. Book of Abstracts of the International Conference “Micro- and Nanoelectronics-2012” (ICMNE-2012), 1.
Flandre, D., Bulteel, O., Gosset, G., Haddad, P.-A., Bernard, S., Rue, B., & Bol, D. (2012). Disruptive ultra-low-leakage design techniques for ultra-low-power CMOS circuits. Proceedings of the CMOS Emerging Technologies Conference. Published. CMOS Emerging Technologies Conference, Vancouver (Canada).
Md Arshad, M. K., Emam, M., Kilchytska, V., Andrieu, F., Flandre, D., & Raskin, J.-P. (2012). RF behavior of undoped channel ultra-thin body with ultra-thin BOX MOSFETs. Proceedings of the 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of papers (SiRF 2012), 105-108. https://doi.org/10.1109/SiRF.2012.6160155
Navarenho de Souza Fino, L., Renaux, C., Flandre, D., & Pinillos Gimenez, S. (2012). Experimental Study of the OCTO SOI nMOSFET to Improve the Device Performance. Proceedings of the Ninth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2012), 55-56.
Makovejev, S., Olsen, S. H., Md Arshad, K., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2012). Improvement of high-frequency FinFET performance by fin width engineering. Proceedings of the IEEE 2012 International SOI Conference (SOI’12), 58-59. https://doi.org/10.1109/SOI.2012.6404381
Fino, L., Renaux, C., Gimenez, S., & Flandre, D. (2012). Using OCTO SOI nMOSFET to Reduce Die Area of Analog Integrated Circuits. Proceedings of the VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012. Published. VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012, Sao Bernardo do Campo (Brazil).
Van Loo, S., Stoukatch, S., Axisa, F., Destiné, J., Van Overstraeten, N., Flandre, D., Lefèvre, O., & Mertens, P. (2012). Low temperature assembly method of microfluidic bio-molecules detection device. Proceedings of the 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D 2012), 181-184. https://doi.org/10.1109/LTB-3D.2012.6238086
de Souza, M., Flandre, D., & Pavanello, M. A. (2012). Comparison of Asymmetric Self-Cascode and Graded-Channel Structures for High Performance Analog SOI MOSFETs. Proceedings of the Ninth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2012). Published. Ninth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EUROSOI 2012), La Grande Motte (France).
de Souza, M., Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid Helium Temperature Analog Operation of Asymmetric Self-Cascode FD SOI MOSFETs. Proceedings of the 2012 IEEE International SOI Conference, 2. https://doi.org/10.1109/SOI.2012.6404377
Kilchytska, V., Raskin, J.-P., & Flandre, D. (2012). UTBB FDSOI and SOI FinFET device assessment for future analog/RF applications. 2012 IEEE International SOI Conference, Napa (USA).
Bol, D., Kilchytska, V., De Vos, J., Andrieu, F., & Flandre, D. (2012). Quasi-Double Gate Mode for Sleep Transistors in UTBB FD SOI Low-Power High-Speed Applications. Proceedings of the 2012 IEEE International SOI Conference, 2. https://doi.org/10.1109/SOI.2012.6404370
Couniot, N., Flandre, D., Francis, L., & Afzalian, A. (2012). Bacteria detection with interdigitated microelectrodes: noise consideration and design optimization. Procedia Engineering of the 2012 EUROSENSORS conference, 188-191. https://doi.org/10.1016/j.proeng.2012.09.115
Francis, L., Druart, S., André, N., Gkotsis, P., Flandre, D., & Raskin, J.-P. (2012). Magnetic sensors enabled by MEMS and SOI technologies. Proceedings of the CMOS Emerging Technologies Conference. Published. CMOS Emerging Technologies Conference, Vancouver (Canada).
de Souza, M., Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid Helium Temperature Operation of Graded-Channel SOI nMOSFETs. ECS Transactions, 49(1), 135-144. (Original work published 2012)
Renauld, M., Kamel, D., Standaert, F.-X., & Flandre, D. (2012). Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box. Lecture Notes in Computer Science, 223-239. https://doi.org/10.1007/978-3-642-23951-9_15
Flandre, D., Kilchytska, V., & Alvarado Pulido, J. J. (2012). Harsh-environment Behaviours and Performances of Advanced Silicon-on-Insulator CMOS Transistors. IEEE EDS Electron Devices Colloquium, IMEC Leuven (Belgium).
De Souza, M., Pavanello, M. A., & Flandre, D. (2012). Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors. Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), 1-4. https://doi.org/10.1109/ICCDCS.2012.6188932
Garduño, S. I., Cerdeira, A., Estrada, M., Kilchytska, V., & Flandre, D. (2012). Analytic modeling of gate tunneling currents for nano-scale double-gate MOSFETs. Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), 1-5. https://doi.org/10.1109/ICCDCS.2012.6188938
Van Overstraeten-Schlögel, N., Lefèvre, O., Couniot, N., & Flandre, D. (2012). A magnetic-based approach for improving the specificity and sensibility of electronics biosensors in diagnostic field. Proceedings of the 2012 IEEE-EMBS Micro- and Nanoengineering in Medicine Conference (MNMC 2012), 1.
Makovejev, S., Olsen, S., Andrieu, F., Poiroux, T., Faynot, O., Flandre, D., Raskin, J.-P., & Kilchytska, V. (2012). On extraction of self-heating features in UTBB SOI MOSFETs. Proceedings of the 13th International Conference on Ultimate Integration on Silicon (ULIS 2012), 109-112. https://doi.org/10.1109/ULIS.2012.6193369
Bouterfa, M., & Flandre, D. (2012). Ultra-Thin Silicon Strip Detectors for Hadrontherapy Beam Monitoring. Proceedings of the IEEE International Conference on Electron Devices and Soli State Circuits (EDSSC 2012), 2.
Van Overstraeten-Schlögel, N., Lefèvre, O., & Flandre, D. (2012). Assessment of different functionalization methods for grafting a protein to an alumina-covered biosensor. Proceedings of the 2012 IEEE-EMBS Micro- and Nanoengineering in Medicine Conference (MNMC 2012), 1.
De Vos, J., Flandre, D., & Bol, D. (2012). A Dual-Mode DC/DC Converter for Ultra-Low-Voltage Microcontrollers. Proceedings of the 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 1-3. https://doi.org/10.1109/SubVT.2012.6404306
Flandre, D., Bulteel, O., Gosset, G., Rue, B., & Bol, D. (2012). Disruptive design techniques based on ultra-low-leakage CMOS blocks for ultra-low-power circuits and microsystems. Proceedings of the VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012. Published. VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012, Sao Bernardo do Campo (Brazil).
Nemer, J. P., De Souza, M., Pavanello, M. A., & Flandre, D. (2012). Analog performance of submicron GC SOI MOSFETs. Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), 1-4. https://doi.org/10.1109/ICCDCS.2012.6188930
Bol, D., De Vos, J., Hocquet, C., Durvaux, F., Botman, F., Boyd, S., Flandre, D., & Legat, J.-D. (2012). A 25MHz 7μW/MHz Ultra-Low-Voltage Microcontroller SoC in 65nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. IEEE International Solid State Circuits Conference. Digest of Technical Papers, 55(1), 490-491. https://doi.org/10.1109/ISSCC.2012.6177104 (Original work published 2012)
Flandre, D., Kilchytska, V., Alvarado, J. J., Boufouss, E. H., Rue, B., Roda Neve, C., Raskin, J.-P., & Francis, L. (2012). Harsh-environment behaviours and performances of advanced Silicon-on-Insulator CMOS sensors, transistors and circuits. VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012, Sao Bernardo do Campo (Brazil).
Kotipalli, R. V. R., Delamare, R., Francis, L., & Flandre, D. (2012). Study of passivation mechanisms induced by negative charge Al2O3 films. Proceedings of the 27th European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC 2012), 3.
Article de journal
Fino, L. N. S., Renaux, C., Flandre, D., & Gimenez, P. (2012). Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits. ECS Transactions, 49(1), 527-534. https://doi.org/10.1149/04901.0527ecst (Original work published 2012)
Afzalian, A., & Flandre, D. (2012). Discrete Random Dopant Fluctuation Impact on Nanoscale Dopant-Segregated Schottky-Barrier Nanowires. IEEE Electron Device Letters, 33(9), 1228-1230. https://doi.org/10.1109/LED.2012.2203350 (Original work published 2012)
Lugo-Muñoz, Muci, J., Ortiz-Conde, A., García-Sánchez, F. J., de Souza, M., Flandre, D., & Pavanello, M. A. (2012). Modeling of Thin-Film Lateral SOI PIN Diodes with an Alternative Multi-Branch Explicit Current Model. Journal of Integrated Circuits and Systems, 7(1), 92-99. (Original work published 2012)
Alvarado Pulido, J. J., Kilchytska, V., Boufouss, E. H., Soto-Cruz, B. S., & Flandre, D. (2012). A compact model for single event effects in PD SOI sub-micron MOSFETs. IEEE Transactions on Nuclear Science, 59(4), 943-949. https://doi.org/10.1109/TNS.2012.2201957 (Original work published 2012)
Arshad, M. K. M., Raskin, J.-P., Kilchytska, V., Andrieu, F., Scheiblin, P., Faynot, O., & Flandre, D. (2012). Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs. IEEE Transactions on Electron Devices, 59(1 (article n°6085605)), 247-251. https://doi.org/10.1109/TED.2011.2172993 (Original work published 2012)
Kilchytska, V., Alvarado, J. J., Put, S., Collaert, N., Simoen, E., Claeys, C., Militaru, O., Berger, G., & Flandre, D. (2012). High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs. Microelectronics Reliability, 52(1), 118-123. https://doi.org/10.1016/j.microrel.2011.08.001 (Original work published 2012)
Kamel, D., Renauld, M., Bol, D., Standaert, F.-X., & Flandre, D. (2012). Analysis of Dynamic Differential Swing Limited Logic for Low-Power Secure Applications. Journal of Low Power Electronics and Applications, 2(1), 98-126. https://doi.org/10.3390/jlpea2010098 (Original work published 2012)
De Vos, J., Flandre, D., & Bol, D. (2012). Pushing Adaptive Voltage Scaling Fully On Chip. Journal of Low Power Electronics, 8(1), 95-105. https://doi.org/10.1166/jolpe.2012.1175 (Original work published 2012)
Makovejev, S., Raskin, J.-P., Md Arshad, M. K., Flandre, D., Olsen, S., Andrieu, F., & Kilchytska, V. (2012). Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs. Solid-State Electronics, 71, 93-100. https://doi.org/10.1016/j.sse.2011.10.027 (Original work published 2012)
André, N., Druart, S., Dupuis, P., Rue, B., Gérard, P., Flandre, D., Raskin, J.-P., & Francis, L. (2012). Dew-based wireless mini module for respiratory rate monitoring. IEEE Sensors Journal, 12(3), 699-706. https://doi.org/10.1109/JSEN.2011.2161668 (Original work published 2012)
Haddad, P.-A., Gosset, G., & Flandre, D. (2012). Design of an Ultra-Low-Power multi-stage AC/DC voltage rectifier and multiplier using a fully-automated and portable design methodology. Journal of Low Power Electronics, 8(2), 197-206. https://doi.org/10.1166/jolpe.2012.1184 (Original work published 2012)
Peruzzi, V. V., Renaux, C., Flandre, D., & Gimenez, S. P. (2012). Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation. ECS Transactions, 49(1), 169-176. https://doi.org/10.1149/04901.0169ECST (Original work published 2012)
Kilchytska, V., Md Arshad, M. K., Makovejev, S., Olsen, S., Andrieu, F., Poiroux, T., Faynot, O., Raskin, J.-P., & Flandre, D. (2012). Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit. Solid-State Electronics, 70, 50-58. (Original work published 2012)
Couniot, N., Afzalian, A., & Flandre, D. (2012). Scaling laws and performance improvements of integrated biosensor microarrays with multi-pixel per spot. Sensors and Actuators B: Chemical : international journal devoted to research and development of physical and chemical transducers, 166-167, 184-192. https://doi.org/10.1016/j.snb.2012.02.038 (Original work published 2012)
Assaad, M., Boufouss, E. H., Gérard, P., Francis, L., & Flandre, D. (2012). Design and characterization of ultra-low-power SOI-CMOS IC temperature level detector. Electronics Letters, 48(14), 842-844. https://doi.org/10.1049/el.2012.1279 (Original work published 2012)
Tang, X., Francis, L., Simonis, P., Haslinger, M., Delamare, R., Deschaume, O., Flandre, D., Defrance, P., Jonas, A., Vigneron, J.-P., & Raskin, J.-P. (2012). Room temperature atomic layer deposition of Al2O3 and replication of butterfly wings for photovoltaic application. Journal of Vacuum Science and Technology. Part A. Vacuum, Surfaces and Films, 30(1), 01A146. https://doi.org/10.1116/1.3669521 (Original work published 2012)
Papier de conférence
De Vos, J., Bol, D., & Flandre, D. (2011). Design methodology for sizing DCDC converters supplying subthreshold circuits. Proceedings of the IEEE Subthreshold Microelectronics Conference. IEEE Subthreshold Microelectronics Conference, Lexington (USA).
Renauld, M., Standaert, F.-X., Veyrat-Charvillon, N., Kamel, D., & Flandre, D. (2011). A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices. Lecture Notes in Computer Science, 6632, 109-128. https://doi.org/10.1007/978-3-642-20465-4_8 (Original work published 2011)
Makovejev, S., Kilchytska, V., Md Arshad, M. K., Flandre, D., Andrieu, F., Faynot, O., Olsen, S., & Raskin, J.-P. (2011). Self-heating and substrate effects in ultra-thin body ultra-thin BOX devices. Proceedings of the 12th International Conference on Ultimate Integration on Silicon – ULIS 2011, 130-133. https://doi.org/10.1109/ULIS.2011.5758009
Pollissard, G., & Flandre, D. (2011). A circuit level 65nm node bulkand SOI technologies comparison for analog amplifiers. Proceedings of the Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011). Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011), Granada (Espagne).
Soung Yee, L., Martin, E., Cortina Gil, E., Renaux, C., & Flandre, D. (2011). Charge Sensitive Amplifier Study in 2μm FD SOI CMOS. Proceedings of the IEEE International SOI Conference (SOI 2011). IEEE International SOI Conference (SOI 2011), Tempe (USA). https://doi.org/10.1109/SOI.2011.6081694
Bol, D., Bernard, S., & Flandre, D. (2011). Pre-Silicon 22/20 nm Compact MOSFET Models for Bulk vs. FD SOI Low-Power Circuit Benchmarks. Proceedings of the IEEE International SOI Conference (SOI 2011). IEEE International SOI Conference (SOI 2011), Tempe (USA). https://doi.org/10.1109/SOI.2011.6081697
Bouterfa, M., Aouadi, K., Bertrand, D., Olbrechts, B., Delamare, R., Raskin, J.-P., Kilchytska, V., Cortina Gil, E., & Flandre, D. (2011). Towards a New Generation of Ultra-Thin P-Type Silicon Strip Detectors for Hadrontherapy Beam Monitoring. Proceedings of ANIMMA. Published. ANIMMA, Ghent (Belgium).
De Souza, M., Rue, B., Flandre, D., & Pavanello, M. A. (2011). Performance of Ultra-Low-Power SOI CMOS Diodes Operating at Low Temperatures. Proceedings of the 219th ECS Meeting. 219th ECS Meeting, Montréal (Canada).
Alvarado, J. J., Boufouss, E. H., Kilchytska, V., & Flandre, D. (2011). A Compact Model for Single Event Effects in PD SOI sub-micron MOSFETs. Proceedings of the Conference on Radiation Effects on Components and Systems (RADECS 2011), 7.
Flandre, D., Bulteel, O., Gosset, G., Rue, B., & Bol, D. (2011). Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems. Proceedings de FTFC 2011, Faible Tension Faible Consommation, Marrakech (Maroc).
Flandre, D. (2011). Extreme-environment behaviours and performances of advanced Silicon-on-Insulator CMOS sensors, transistors and circuits. Proceedings of the Second International Conference on Advancements in Nuclear Instrumentation, Measurement Methods and their Applications (ANIMMA’11). The Second International Conference on Advancements in Nuclear Instrumentation, Measurement Methods and their Applications (ANIMMA’11), Ghent (Belgium).
Bouterfa, M., Aouadi, K., Bertrand, D., Olbrechts, B., Raskin, J.-P., Delamare, R., Cortina Gil, E., & Flandre, D. (2011). Hadrontherapy beam monitoring: towards a new generation of ultra-thin p-type silicon strip detectors. Proceedings of the The Second International Conference on Advancements in Nuclear Instrumentation, Measurement Methods and their Applications – ANIMMA’11, paper INV30.
Renauld, M., Kamel, D., Standaert, F.-X., & Flandre, D. (2011). Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box. Lecture Notes in Computer Science, 6917, 223-239. (Original work published 2011)
Kilchytska, V., Md Arshad, M. K., Makojev, S., Olsen, S., Andrieu, F., Faynot, O., Raskin, J.-P., & Flandre, D. (2011). Ultra-thin body and BOX SOI Analog Figures of Merit. Proceedings of the Sixth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits – EuroSOI’11, 143-144.
Delamare, R., Yedji, M., Demarche, J., Terwagne, G., & Flandre, D. (2011). High density array of size controlled silicon nanodots for all Si solar cells. Proceedings of the 26th European Photovoltaic solar energyconference. 26th European Photovoltaic solar energyconference, Hambourg (Allemagne).
De Vos, J., Flandre, D., & Bol, D. (2011). Variability and ripple analysis of an on-chip all-digital AVS system. VARI Workshop on CMOS Variability, Grenoble (France).
Makovejev, S., Raskin, J.-P., Flandre, D., Olsen, S., Andrieu, F., Poiroux, T., & Kilchytska, V. (2011). Comparison of Small-Signal Output Conductance Frequency Dependence in UTBB SOI MOSFETs with and without Ground Plane. Proceedings of the IEEE International SOI Conference. Published. IEEE International SOI Conference, Tempe (USA). https://doi.org/10.1109/SOI.2011.6081717
Dupuis, P., Van Overstraeten, N., Raskin, J.-P., Francis, L., & Flandre, D. (2011). Some mitigations for unequal data variance in linear regression. Proceedings of the AMCTM conference. Published. AMCTM conference, Göteborg (Sweden).
André, N., Francis, L., Raskin, J.-P., Nachtergaele, P., Cases, S., Paquay, S., De Batselier, E., & Flandre, D. (2011). The integrated design of a MEMS-based flow-sensor system. Proceedings of the The 9th International Nanotech Symposium & Exhibition in Korea - NANO KOREA 2011. Published. The 9th International Nanotech Symposium & Exhibition in Korea - NANO KOREA 2011, Kintex (Korea).
Gkotsis, P., Kilchytska, V., Militaru, O., Tang, X., Raskin, J.-P., Flandre, D., & Francis, L. (2011). Neutron and gamma radiation effects on MEMS structures. International conference EuroSensors XXV, paper #1345.
Tang, X., Francis, L., Haslinger, M., Delamare, R., Flandre, D., Simonis, P., Vigneron, J.-P., Deschaume, O., Jonas, A., & Raskin, J.-P. (2011). Replication of butterfly wings by ALD and nanoimprint for production of Si solar cells with high light absorption surface. Proceedings of the 11th International Conference on Atomic Layer Deposition – ALD 2011. Published. 11th International Conference on Atomic Layer Deposition – ALD 2011, Cambridge, Massachusetts (USA).
André, N., Francis, L., Rue, B., Druart, S., Dupuis, P., Flandre, D., & Raskin, J.-P. (2011). Ultra low power SOI transducer for flow and dew-based humidity sensing. Proceedings of the 2011 CMOS Emerging Technologies Workshop, session 1-D, paper 6.
André, N., Rue, B., Scheen, G., Francis, L., Flandre, D., & Raskin, J.-P. (2011). Ultra Low Power 3-D flow meter in monolithic SOI technology. Proceedings of the 219th Electrochemical Society Meeting – ECS 2011, paper 1459.
Flandre, D., Kilchytska, V., Alvarado Pulido, J. J., Boufouss, E. H., Assaad, M., Rue, B., Roda Neve, C., Raskin, J.-P., & Francis, L. (2011). Extreme-environment behaviors and performances of advanced Silicon-on-Insulator CMOS sensors, transistors and circuits. 2nd International Conference on Advancements in Nuclear Instrumentation, Measurement Methods and their Applications (ANIMMA 2011), Ghent (Belgium).
Rudenko, C., Kilchytska, V., Md Arshad, M. K., Raskin, J.-P., Nazarov, A., & Flandre, D. (2011). Impact of mobility variation on threshold voltage extraction by transconductance change and gm/Id methods and its demonstration on advanced SOI MOSFETs. Proceedings of the Sixth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits – EuroSOI’11, 25-26.
Bol, D., Hocquet, C., De Vos, J., Durvaux, F., Botman, F., Flandre, D., & Legat, J.-D. (2011). Design techniques for reliable timing closure in ULV SoCs. 2011 Subthreshold Microelectronics Conference, Lexington (MA).
Gosset, G., Bulteel, O., Baijot, P., & Flandre, D. (2011). Ultra-High-Efficiency Co-Integrated Photovoltaic Energy Scavenger. Proceedings of SOI Conference 2011, Tempe (USA).
Afzalian, A., & Flandre, D. (2011). Transport-Confined Multi-Barrier FETs: A New Paradigm for Low-Leakage High On-Current Transistors. Trans. of 219th ECS Symp.:Advanced Semiconductor-on-Insulator Technology and Related Physics 15, 35(5), 295-300. https://doi.org/10.1149/1.3570809 (Original work published 2011)
De Souza, M., Flandre, D., & Pavanello, M. A. (2011). Asymmetric Self-Cascode Configuration to Improve the Analog Performance of SOI nMOS Transistors. Proceedings of the IEEE International SOI Conference (SOI 2011), 1-2. https://doi.org/10.1109/SOI.2011.6081716
Van Overstraeten, N., Dupuis, P., Lefèvre, O., Magnin, D., Demoustier, S., Jonas, A., Heusdens, B., Stoukatch, S., Van Loo, S., & Flandre, D. (2011). Immunoassay using a biofunctionnalized alumina-coated capacitive biosensor: towards a detection of the H5N1 Influenza virus in microfluidics. Proceedings of the International Bio-Sensing Technology Conference (BITE). International Bio-Sensing Technology Conference (BITE), Amsterdam (Pays-Bas).
Olbrechts, B., Rue, B., Flandre, D., & Raskin, J.-P. (2011). Innovative Frequency Output Pressure Sensor with Single SOI NMOSFET Suspended Transducer. Proceedings of the IEEE International SOI Conference(SOI 2011), 1-2. https://doi.org/10.1109/SOI.2011.6081790
Rudenko, T., Kilchytska, V., Md Arshad, M. K., Raskin, J.-P., Nazarov, A., & Flandre, D. (2011). Influence of drain voltage on MOSFET threshold voltage determination by transconductance change and gm/Id methods. Proceedings of the 12th International Conference on Ultimate Integration on Silicon – ULIS 2011, 150-153.
Rue, B., Olbrechts, B., Raskin, J.-P., & Flandre, D. (2011). A SOI CMOS smart strain sensor. Proceedings of the IEEE International SOI Conference (SOI 2011), 1-2. https://doi.org/10.1109/SOI.2011.6081791
Kilchytska, V., Andrieu, F., Faynot, O., & Flandre, D. (2011). High-temperature perspectives of UTB SOI MOSFETs. Proceedings of the 2011 Ultimate Integration of Silicon Conference (ULIS 2011). Ultimate Integration of Silicon Conference (ULIS), Cork (Irlande). https://doi.org/10.1109/ULIS.2011.5758013
Alvarado Pulido, J. J., Kilchytska, V., Boufouss, E. H., & Flandre, D. (2011). Characterization and modeling of single event transients in LDMOS-SOI FETs. Proceedings of the 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis 2011. 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Bordeaux.
Bulteel, O., Van Overstraeten, N., Dupuis, P., & Flandre, D. (2011). Complete Microsystem Using SOI Photodiode for DNA Concentration Measurement. Proceedings of the Biomedical Circuits and Systems Conference (BioCAS). Biomedical Circuits and Systems Conference (BioCAS), Paphos (Grèce).
Olbrechts, B., Rue, B., Pardoen, T., Flandre, D., & Raskin, J.-P. (2011). A novel approach for active pressure sensors in thin film SOI technology. Proceedings of the International conference Eurosensors XXV. Published. International conference Eurosensors XXV, Athènes (Grèce).
Van Overstraeten, N., Dupuis, P., Lefevre, O., Magnin, D., Demoustier, S., Jonas, A., Stoukatch S., Van Loo, S., & Flandre, D. (2011). Immunoassay using a biofunctionnalized alumina-coated capacitive biosensor: towards a detection of the H5N1 Influenza virus in microfluidics. 10th National Day on Biomedical engineering and annual symposium of the IEEE EMBS Benelux Chapter, Gent, Belgium.
Boufouss, E. H., Francis, L., Gérard, P., Assaad, M., & Flandre, D. (2011). Ultra Low Power CMOS Circuits Working in Subthreshold Regime for High Temperature and Radiation Environments. International Conference and Exhibition on High Temperature Electronics Network (HiTEN), Oxford (Royaume-Uni).
Druart, S., André, N., Flandre, D., & Francis, L. (2011). CMOS Test Circuit Architecture for the Extraction of Fluid Propertiesusing Interdigitated Electrodes Microsensors. Transducers 2011, Beijing (China).
Article de journal
Kilchytska, V., Alvarado, J., Militaru, O., Berger, G., & Flandre, D. (2011). Effects of high-energy neutrons on advanced SOI MOSFETs. Advanced Materials Research, 276(276.95), 95-105. https://doi.org/10.4028/www.scientific.net/AMR.276.95 (Original work published 2011)
Olbrechts, B., Rue, B., Pardoen, T., Flandre, D., & Raskin, J.-P. (2011). A novel Approach for Active Pressure Sensors in Thin Film SOI Technology. Procedia Engineering, 25, 43-46. https://doi.org/10.1016/j.proeng.2011.12.011 (Original work published 2011)
Roda Neve, C., Kilchytska, V., Alvarado, J. J., Lederer, D., Militaru, O., Flandre, D., & Raskin, J.-P. (2011). Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer. Microelectronics Reliability, 51(2), 326-331. https://doi.org/10.1016/j.microel.2010.07.153 (Original work published 2011)
Carta, R., Thoné, J., Gosset, G., Cogels, G., Flandre, D., & Puers, R. (2011). A self-tuning inductive powering system for biomedical implants. Procedia Engineering, 25, 1585-1588. https://doi.org/10.1016/j.proeng.2011.12.392 (Original work published 2011)
Rudenko, T., Kilchytska, V., Arshad, M. K., Raskin, J.-P., Nazarov, A., & Flandre, D. (2011). On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II—Effect of Drain Voltage. IEEE Transactions on Electron Devices, 99, 1-9. https://doi.org/10.1109/TED.2011.2168227 (Original work published 2011)
Afzalian, A., Colinge, J.-P., & Flandre, D. (2011). Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current. Solid-State Electronics, 59(1), 50-61. https://doi.org/10.1016/j.sse.2011.01.016 (Original work published 2011)
Reckinger, N., Tang, X., Dubois, E., Larrieu, G., Flandre, D., Raskin, J.-P., & Afzalian, A. (2011). Low temperature tunneling current enhancement in silicide/Si Schottky contacts with nanoscale barrier width. Applied Physics Letters, 98(11), 112102. https://doi.org/10.1063/1.3567546 (Original work published 2011)
Gosset, G., & Flandre, D. (2011). Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers. I E E E Journal on Emerging and Selected Topics in Circuits and Systems, 1(2), 141-149. https://doi.org/10.1109/JETCAS.2011.2158357 (Original work published 2011)
de Souza, M., Bulteel, O., Flandre, D., & Pavanello, M. A. (2011). Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short Wavelengths. Journal of Integrated Circuits and Systems, 6(1), 107-113. (Original work published 2011)
André, N., Rue, B., Scheen, G., Francis, L., Flandre, D., & Raskin, J.-P. (2011). Ultra Low Power 3-D Flow Meter in Monolithic SOI Technology. Journal of the Electrochemical Society, 35(5), 319-324. https://doi.org/10.1149/1.3570812 (Original work published 2011)
Tang, X., Flandre, D., Raskin, J.-P., Nizet, Y., Moreno-Hagelsieb, L., Pampin, R., & Francis, L. (2011). Rapid and selective detection of Staphylococcus aureus using insulated substrate impedance transducers. Sensors and Actuators, B(156), 578-587. (Original work published 2011)
Tang, X., Krzeminski, C., Lecavalier des Etangs-Levallois, A., Chen, Z., Dubois, E., Kasper, E., Karmous, A., Reckinger, N., Flandre, D., Francis, L., Colinge, J.-P., & Raskin, J.-P. (2011). Energy-Band Engineering for Improved Charge Retention in Fully Self-Aligned Double Floating-Gate Single-Electron Memories. Nano Letters : a journal dedicated to nanoscience and nanotechnology, 11(11), 4520-4526. https://doi.org/10.1021/nl202434k (Original work published 2011)
Tang, X., Flandre, D., Raskin, J.-P., Nizet, Y., Moreno Hagelsieb, L., Pampin, R., & Francis, L. (2011). A new interdigitated array microelectrode-oxide-silicon sensor with label-free, high sensitivity and specificity for fast bacteria detection. Sensors and Actuators B: Chemical : international journal devoted to research and development of physical and chemical transducers, 156(2), 578-587. https://doi.org/10.1016/j.snb.2011.02.002 (Original work published 2011)
Kilchytska, V., Alvarado, J., Collaert, N., Rooyackers, R., Put, S., Simoen, E., Claeys, C., & Flandre, D. (2011). Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs. Solid-State Electronics, 59(1), 50-61. https://doi.org/10.1016/j.sse.2011.01.008 (Original work published 2011)
Yedji, M., Demarche, J., Terwagne, G., Delamare, R., Flandre, D., Barba, D., & Koshel, D. (2011). Method for fabricating third generation photovoltaic cells based on Si quantum dots using ion implantation into SiO2. Journal of Applied Physics, 109(8), 6 pages. https://doi.org/10.1063/1.3575325 (Original work published 2011)
Afzalian, A., & Flandre, D. (2011). Computational study of dopant segregated nanoscale Schottky barrier MOSFETs for steep slope, low SD-resistance and high on-current gate-modulated resonant tunneling FETs. Solid-State Electronics, 65-66(1), 123-129. https://doi.org/10.1016/j.sse.2011.06.017 (Original work published 2011)
Conde, Cerdeira, Pavanello, Kilchytska, V., & Flandre, D. (2011). 3D simulation of triple-gate MOSFETs with different mobility regions. Microelectronic Engineering, 88(7), 1633-1636. https://doi.org/10.1016/j.mee.2011.03.013 (Original work published 2011)
Garduno, S. I., Cerdeira, A., Estrada, M., Alvarado, J. J., Kilchytska, V., & Flandre, D. (2011). Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors. Journal of Applied Physics, 109(8). https://doi.org/10.1063/1.3575324 (Original work published 2011)
Olbrechts, B., Rue, B., Pardoen, T., Flandre, D., & Raskin, J.-P. (2011). Routes towards novel active pressure sensors in SOI technology. Advanced Materials Research, 276, 145-155. https://doi.org/10.4028/www.scientific.net/AMR.276.145 (Original work published 2011)
Rudenko, T., Kilchytska, V., Arshad, M. K. M., Raskin, J.-P., Nazarov, A., & Flandre, D. (2011). On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility. IEEE Transactions on Electron Devices, 99, 1-8. https://doi.org/10.1109/TED.2011.2168226 (Original work published 2011)
Alvarado, J. J., Kilchytska, V., Boufouss, E. H., & Flandre, D. (2011). Characterization and modelling of single event transients in LDMOS-SOI FETs. Microelectronics Reliability, 51(9-11), 2004-2009. https://doi.org/10.1016/j.microrel.2011.07.082 (Original work published 2011)
Hocquet, C., Kamel, D., Regazzoni, F., Legat, J.-D., Flandre, D., Bol, D., & Standaert, F.-X. (2011). Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. Journal of Cryptographic Engineering, 1(1), 79-86. https://doi.org/10.1007/s13389-011-0005-z (Original work published 2011)
Cortina Gil, E., Soung Yee, L., Renaux, C., & Flandre, D. (2011). TRAPPISTe pixel sensor with 2 µm SOI technology. Nuclear Instruments & Methods in Physics Research. Section A: Accelerators, Spectrometers, Detectors, and Associated Equipment, 663, 19-21. https://doi.org/10.1016/j.nima.2010.06.109 (Original work published 2011)
Gkotsis, P., Kilchytska, V., Bhaskar, U. K., Militaru, O., Tang, X., Fragkiadakis, C., Kirby, P. B., Raskin, J.-P., Flandre, D., & Francis, L. (2011). Neutron and gamma radiation effects on MEMS structures. Procedia Engineering, 25, 172-175. https://doi.org/10.1016/j.proeng.2011.12.043 (Original work published 2011)
Chapitre de livre
Afzalian, A., Colinge, J.-P., & Flandre, D. (2011). Gate Modulated Resonant Tunneling Transistor (RT-FET): Performance Investigation of a Steep Slope, High On-Current device through 3D Non-Equilibrium Green Function simulations. In Semiconductor-On-Insulator Materials for Nano-Electronics Applications (p. p. 201-214). Springer.
André, N., Francis, L., Rue, B., Renaux, C., Flandre, D., & Raskin, J.-P. (2011). Artificial microbeams for sensing air flow, temperature and humidity by combining MEMS and CMOS technologies. In Kris Iniewski (ed.), Optical, Acoustic, Magnetic, and Mechanical Sensor Technologies. CRC Press.
Rudenko, T., Kilchytska, V., Raskin, J.-P., Nazarov, A., & Flandre, D. (2011). Special features of the back-gate effects in ultra-thin body SOI MOSFETs. In Nazarov, A., Colinge, J.-P., Balestra, F., Raskin, J.-P., Gamiz, F., Lysenko, V.S. (Eds.) (ed.), Semiconductor-On-Insulator Materials for NanoElectronics Applications (p. p. 323-343). Springer-Verlag.
Kilchytska, V., Raskin, J.-P., & Flandre, D. (2011). Specific features of MuGFETs behavior at high temperatures in a wide frequency range. In N. Collaert (ed.), CMOS Nanoelectronics: Innovative Devices, Architectures and Applications. Pan Stanford Publishers.
Afzalian, A., & Flandre, D. (2011). Design of Thin-Film Lateral SOI PIN Photodiodes with up to Tens of GHz Bandwidth. In Gian Franco Dalla Betta (ed.), Advances in Photodiodes. InTech.
Bulteel, O., Van Overstraeten, N., Afzalian, A., Dupuis, P., Jeumont, S., Irenge Mwana Wa Bene, L., Ambroise, J., Macq, B., Gala, J.-L., & Flandre, D. (2011). Low-Wavelengths SOI CMOS Photosensors for Biomedial Applications. In Anthony Laskovski (ed.), Biomedical Engineering, Trends in Electronics, Communications and Software (pp. 257-276). InTech Europe.
Raskin, J.-P., Francis, L., & Flandre, D. (2011). Sensing and MEMS Devices in Thin-Film SOI MOS Technology. In A. Nazarov et al. (eds.) (ed.), Semiconductor-On-Insulator Materials for Nanoelectronics Applications, Engineering Materials (p. p. 355-392). Springer-Verlag. https://doi.org/10.1007/978-3-642-15868-1_20
Papier de conférence
Kilchytska, V., Flandre, D., Alvarado, J., Collaert, N., Rooyakers, R., Militaru, O., & Berger, G. (2010). Total-Dose Effects Caused by High-Energy Neutrons and gamma-Rays in Multiple-Gate FETs. IEEE Transactions on Nuclear Science, 57(4), 1764-1770. https://doi.org/10.1109/TNS.2009.2037419 (Original work published 2010)
Garduno, I., Cerdeira, A., Estrada, M., Kilchytska, V., & Flandre, D. (2010). Modeling of main leakage currents and their contribution to channel current in Fin-FETs. Proceedings of the 27th International Conference on Microelectronics (MIEL 2010), 99-102. https://doi.org/10.1109/MIEL.2010.5490523
Conde, J., Cerdeira, A., Pavanello, M., Kilchytska, V., & Flandre, D. (2010). 3D Simulation of Triple-Gate MOSFETs. Proceedings of the 27th International Conference on Microelectronics (MIEL 2010), 409-411. https://doi.org/10.1109/MIEL.2010.5490454
Boufouss, E. H., Alvarado Pulido, J. J., & Flandre, D. (2010). Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM. Proceedings of the HITEC Conference, 77-82.
Kilchytska, V., Alvarado, J. J., Militaru, O., Berger, G., & Flandre, D. (2010). Effects of high–energy neutrons on advanced SOI MOSFETs. Proceedings of the 6th International SemOI Workshop “Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices”,. 6th International SemOI Workshop “Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices”, Kiev (Ukraine).
Mallat, A., Gérard, P., Drouguet, M., Keshmiri, F., Oestges, C., Craeye, C., Flandre, D., & Vandendorpe, L. (2010). Testbed for IR-UWB based ranging and positioning: Experimental performance and comparison to CRLBs. Proceedings 5th International Symposium on Wireless Pervasive Computing, 163-168. https://doi.org/10.1109/ISWPC.2010.5483707
de Souza, M., Emam, M., Vanhoenacker-Janvier, D., Raskin, J.-P., Flandre, D., & Pavanello, M. A. (2010). Comparison between the behavior of submicron Graded-Channel SOI nMOSFETs with Fully- and Partially-Depleted operations in a wide temperature range. Proceedings of the 2010 IEEE International SOI Conference, 82-83.
Gosset, G., Pollissard, G., Rue, B., Bol, D., & Flandre, D. (2010). Disruptive ultra-low-power SOI CMOS circuits towards µW medical sensor implants. Proceedings of the IEEE International Silicon on Insulator Conference (SOI 2010), 1-2. https://doi.org/10.1109/SOI.2010.5641370
Rudenko, T., Flandre, D., Kilchytska, V., Burignat, S., Raskin, J.-P., Andrieu, F., Faynot, O., Le Tiec, Y., Landry, K., Nazarov, A., & Lysenko, V. S. (2010). Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides. Solid-State Electronics, 54(2), 164-170. https://doi.org/10.1016/j.sse.2009.12.014 (Original work published 2010)
Burignat, S., Flandre, D., Arshad, M. K., Kilchytska, V., Andrieu, F., Faynot, O., & Raskin, J.-P. (2010). Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel. Solid-State Electronics, 54(2), 213-219. https://doi.org/10.1016/j.sse.2009.12.021 (Original work published 2010)
Rudenko, T., Kilchytska, V., Raskin, J.-P., Andrieu, F., Faynot, O., Le Tiec, Y., Landry, K., Nazarov, A., & Flandre, D. (2010). Special Features of the Back-Gate Effects in UTB SOI MOSFETs. Proceedings of the 6th International SemOI Conference and 1st Ukrainian-French Seminar “Semiconductor-on-Insulator materials, devices and circuits: physics, technology and diagnostics”, 18-19.
Afzalian, A., Colinge, J.-P., & Flandre, D. (2010). Variable Barrier Resonant Tunneling Transistor: A New Path Towards Steep Slope and High On-Current? Proceedings of the 2010 EUROSOI Conference, p. 109-110.
Alvarado Pulido, J. J., Kilchytska, V., Boufouss, E. H., & Flandre, D. (2010). Modeling of Single Event Transients and Total Dose in Partially Depleted SOI CMOS Circuits. Proceedings of EUROSOI 2010. EUROSOI 2010, Grenoble (France).
de Souza, M., Bulteel, O., Flandre, D., & Pavanello, M. (2010). Electrical Characterization of SOI Solar Cells in a Wide Temperature Range. Proceedings of the IEEE International Silicon on Insulator Conference (SOI 2010), 1-2.
Pollissard-Quatremere, G., Gosset, G., & Flandre, D. (2010). Analog design oriented ultra-deep-submicron CMOS technology analysis. Proceedings of the 6th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2010), 4.
Alvarado Pulido, J. J., Kilchytska, V., Boufouss, E. H., & Flandre, D. (2010). Compact Model for Single Event Transients and Total Dose Eects at High Temperatures for Partially Depleted SOI MOSFETs. Proceedings of the 21st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2010). 21st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2010), Gaeta.
Druart, S., Flandre, D., & Francis, L. (2010). A Methodology for the Simulation of MEMS Spiral Inductances used as Magnetic Sensors. Proceedings of the COMSOL Conference. COMSOL Conference, Paris (France).
Francis, L., André, N., Rue, B., Dupuis, P., Gérard, P., Bouterfa, M., Moreno Hagelsieb, L., Flandre, D., & Raskin, J.-P. (2010). Wireless humidity sensing: CMOS fabrication, interfaces, packaging and various applications from weather to re-education. Proceedings of the Ecole d’hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes – FETCH’10, Tutorial 1.
Tang, X., Francis, L., Raskin, J.-P., & Flandre, D. (2010). Rapid and Selective Detection of Staphylococcus Aureus Using Insulated Substrate Impedance Transducers. Proceedings of the BIT’s 3rd World Congress of Industrial Biotechnology 2010 (ibio-2010), Track 4.2, p. 292.
Moreno Hagelsieb, L., Nizet, Y., Tang, X., Bulteel, O., Van Overstaeten-Schlögel, N., André, N., Dupuis, P., Raskin, J.-P., Fontayne, P. A., Gala, J.-L., Francis, L., & Flandre, D. (2010). Miniaturized and low cost innovative detection systems for medical and environmental applications. Proceedings of the IEEE 2nd Circuits and Systems for Medical and Environmental Applications Workshop - CASME 2010, Article n°5706682. https://doi.org/10.1109/CASME.2010.5706682
Moreno Hagelsieb, L., Tang, X., Bulteel, O., Nizzet, Y., André, N., Gérard, P., Dupuis, P., Francis, L., Raskin, J.-P., & Flandre, D. (2010). Low-power/high-temperature sensors and MEMS in SOI technology. Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010, 165-168.
Kilchytska, V., Alvarado Pulido, J. J., Put, S., Collaert, N., Simoen, E., Claeys, C., Militaru, O., Berger, G., & Flandre, D. (2010). High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs. Proceedings of the 21st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2010), 6.
Kilchytska, V., Flandre, D., Alvarado, J., Collaert, N., Rooyakers, R., Militaru, O., & Berger, G. (2010). Effect of high-energy neutrons on MuGFETs. Solid-State Electronics, 54(2), 196-204. https://doi.org/10.1016/j.sse.2009.12.019 (Original work published 2010)
Md Arshad, M. K., Raskin, J.-P., Kilchytska, V., Flandre, D., Faynot, O., Scheiblin, P., & Andrieux, F. (2010). Improved DIBL in Ultra Thin Body SOI MOSFETs with Ultra Thin Buried Oxide and inverted substrate. Proceedings of the ULtimate Integration on Silicon - ULIS’10, 113-116.
Bol, D., Legat, J.-D., Hocquet, C., & Flandre, D. (2010). Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. Proceedings of the IEEE International Symposium on Circuits and Systems. ISCAS 2010, 1484-1487. https://doi.org/10.1109/ISCAS.2010.5537352
Afzalian, A., Colinge, J.-P., & Flandre, D. (2010). Variable Barrier Resonant Tunneling Transistor: Performance investigation of a Steep Slope, High On-Current device. Proceedings of the 2010 SemOI Conference, 2.
Afzalian, A., & Flandre, D. (2010). Breaching the kT/q limit with dopant segregated Schottky barrier resonant tunneling MOSFETs: A computationnal study. Proceedings of the European Solid-State Device Research Conference (ESSDERC 2010), p. 376-379. https://doi.org/10.1109/ESSDERC.2010.5618206
Bol, D., Hocquet, C., Flandre, D., & Legat, J.-D. (2010). The Detrimental Impact of Negative Celsius Temperature on Ultra-Low-Voltage CMOS Logic. Proceedings of the ESSCIRC 2010, p. 522 - 525.
Gosset, G., Pollissard, G., & Flandre, D. (2010). An Extended CAD Methodology for sizing Low-Power Low-Voltage OTA Architectures in Decanometric Technologies. Proceedings of the 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD 2010), 1-4.
Al Kadi Jazairli, M., Mallat, A., Vandendorpe, L., & Flandre, D. (2010). An Ultra-Low-Power frequency-tunable UWB pulse generator using 65nm CMOS technology. Proceedings of ICUWB, IEEE International Conference on Ultra-Wideband, 1-4.
Kamel, D., Hocquet, C., Standaert, F.-X., Flandre, D., & Bol, D. (2010). Glitch-Induced Within-Die Variations of Dynamic Energy in Voltage-Scaled Nano-CMOS Circuits. Proceedings of ESSCIRC, European Solid-State Circuits Conference. ESSCIRC, European Solid-State Circuits Conference, Valencia (Spain).
Kilchytska, V., Alvarado Pulido, J. J., Collaert, N., Rooyakers, R., Put, S., Claeys, C., & Flandre, D. (2010). Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs. Proceedings of the Sixth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2010), p. 119-120.
Olbrechts, B., Rue, B., Pardoen, T., Flandre, D., & Raskin, J.-P. (2010). Routes towards novel active pressure sensors in SOI technology. Proceedings of the 6th International SemOI Conference and 1st Ukrainian-French Seminar “Semiconductor-on-Insulator materials, devices and circuits: physics, technology and diagnostics”, p. paper 36.
André, N., Francis, L., Druart, S., Dupuis, P., Flandre, D., & Raskin, J.-P. (2010). Portable wireless microsensing system for human breath monitoring. Proceedings of the 2010 CMOS Emerging Technologies Workshop, Session 2E: Wireless, paper 7.
Bouterfa, M., Gosset, G., Gérard, P., Francis, L., & Flandre, D. (2010). A wireless low power readout circuit for capacitive breathing sensor. Proceedings of the 9th Belgian Natioanl Day on Biomedical Engineering. 9th Belgian National Day on Biomedical Engineering, Brussels (Belgium).
Assaad, M., Gérard, P., Francis, L., & Flandre, D. (2010). Ultra Low Power, Harsh Environment SOI-CMOS Design of Temperature Sensor Based Threshold Detection and Wake-Up IC. Proceedings of the IEEE International SOI Conference 2010. IEEE International Silicon on Insulator Conference (SOI 2010), San Diego (CA/USA).
Article de journal
Alvarado, J., Flandre, D., Boufouss, E. H., & Kilchytska, V. (2010). Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs. Microelectronics Reliability, 50(9-11), 1852-1856. https://doi.org/10.1016/j.microrel.2010.07.040 (Original work published 2010)
Simoen, E., Put, S., Claeys, C., Kilchytska, V., Alvarado Pulido, J. J., & Flandre, D. (2010). Study of neutron irradiation effects on SOI and strained SOI MuGFETs assessed by low-frequency noise. ECS Transactions, 31(1), 43-50. https://doi.org/10.1149/1.3474140 (Original work published 2010)
de Souza, M., Bulteel, O., Flandre, D., & Pavanello, M. (2010). Analysis of Lateral SOI PIN Diodes for the Detection of Blue and UV Wavelengths in a Wide Temperature Range. ECS Transactions, 31(1), 199-206. (Original work published 2010)
André, N., Druart, S., Gérard, P., Pampin, R., Moreno Hagelsieb, L., Kezai, T., Francis, L., Flandre, D., & Raskin, J.-P. (2010). Miniaturized wireless sensing system for real-time breath activity recording. IEEE Sensors Journal, 10(1), 178-184. https://doi.org/10.1109/JSEN.2009.2035666 (Original work published 2010)
de Souza, M., Rue, B., Flandre, D., & Pavanello, M. (2010). Thin-Film Lateral SOI PIN Diodes for Thermal Sensing Reaching the Cryogenic Regime. Journal of Integrated Circuits and Systems, 5(2), 160-167. (Original work published 2010)
Bawedin, M., Cristoloveanu, S., Flandre, D., & et al. (2010). Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications. Solid-State Electronics, 54(2), 104-114. https://doi.org/10.1016/j.sse.2009.12.004 (Original work published 2010)
Bol, D., Flandre, D., & Legat, J.-D. (2010). Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic-Mitigation at Technology and Circuit Levels. A C M Transactions on Design Automation of Electronic Systems, 16(1), 26 pages. https://doi.org/10.1145/1870109.1870111 (Original work published 2010)
Lugo-Munoz, D., de Souza, M., Pavanello, M., Flandre, D., Muci, J., Ortiz-Conde, A., & Garcia Sanchez, F. J. (2010). Parameter Extraction in Quadratic Exponential Junction Model with Series Resistance using Global Lateral Fitting. ECS Transactions, 31(1), 369-376. (Original work published 2010)
Flandre, D., Kilchytska, V., & Rudenko, T. (2010). Gm/Id Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs with nonlinear behavior above threshold. IEEE Electron Device Letters, 31(9), 930-932. https://doi.org/10.1109/LED.2010.2055829 (Original work published 2010)
Bulteel, O., Afzalian, A., & Flandre, D. (2010). Fully integrated blue/UV SOI CMOS photosensor for biomedical and environmental applications. Analog Integrated Circuits and Signal Processing, 65(3), 399-405. https://doi.org/10.1007/s10470-009-9402-y (Original work published 2010)
Hassoune, I., Flandre, D., O’Connor, I., & Legat, J.-D. (2010). ULPFA: A New Efficient Design of a Power-Aware Full Adder. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 57(8), 2066-2074. https://doi.org/10.1109/TCSI.2008.2001367 (Original work published 2010)
Dupuis, P., André, N., Gérard, P., Flandre, D., Raskin, J.-P., & Francis, L. (2010). A fast and robust algorithm to assess respiratory frequency in real-time. Procedia Engineering, 5, 576-579. https://doi.org/10.1016/j.proeng.2010.09.175 (Original work published 2010)
André, N., Rue, B., Van Vynckt, D., Francis, L., Flandre, D., & Raskin, J.-P. (2010). Ultra Low Power flow-to-frequency SOI MEMS transducer. Procedia Engineering, 5, 540-543. https://doi.org/10.1016/j.proeng.2010.09.166 (Original work published 2010)
Brevet
Proost, J., Santoro, R., Soumillion, P., Flandre, D., & Deschuyteneer, G. (2010). Genetically modified bacteriophage, biosensor containing same, and method of use (Patent No. WO 2010142532).
Bol, D., Flandre, D., & Legat, J.-D. (2010). Ultra-low-power circuits (Patent No. US20080598365).
Gosset, G., Flandre, D., Delmée, G., & Rue, B. (2010). Network architecture for wirelessly interfacing sensors at ultra low power (Patent No. US 12/863,926).
Chapitre de livre
Kilchytska, V., Flandre, D., & Raskin, J.-P. (2010). Wide Frequency Band Characterization. In Francis Balestra (eds) (ed.), Nanoscale CMOS: Innovative Materials, Modeling and Characterization (p. 672 pages). Wiley-ISTE. https://doi.org/10.1002/9781118621523.ch17
Papier de conférence
Rue, B., Bulteel, O., Flandre, D., de Souza, M., & Pavanello, M. A. (2009). SOI Lateral PIN Diodes for Temperature and UV Sensing in Very Harsh Environments. Proceedings of HiTEN′09, IMAPS International Conference on High Temperature Electronics Network. IMAPS International Conference on High Temperature Electronics Network (HiTEN′09), Oxford/UK.
Kamel, D., Standaert, F.-X., Bol, D., & Flandre, D. (2009). Comparison of ultra-low-power and static CMOS full adders in 0.15 mu m FD SOI CMOS. 2009 IEEE International SOI Conference, 2 pp. https://doi.org/10.1109/SOI.2009.5318751
Bulteel, O., & Flandre, D. (2009). Optimization of blue/UV sensors using p-i-n photodiodes in thin-film SOI technology. Proceedings of the International Symposium on Silicon on Insulator Technology and Devices. International Symposium on Silicon on Insulator Technology and Devices 2009, San Francisco (USA).
de Souza, M., Flandre, D., & Pavanello, M. A. (2009). Performance of Common-Source, Cascode and Wilson Current Mirrors Implemented with Graded Channel SOI nMOSFETs in a Wide Temperature Range. Proceedings of the International Symposium on Silicon on Insulator Technology and Devices. International Symposium on Silicon on Insulator Technology and Devices, San Francisco (USA).
de Souza, M., Flandre, D., Martino, J. A., Simoen, E., Claeys, C., & Pavanello, M. A. (2009). Impact of temperature reduction and channel engineering on the linearity of FD SOI nMOSFETs. Proceedings of the EUROSOI Conference 2009. EUROSOI Conference 2009, Göteborg (Sweden).
Alvarado Pulido, J. J., Kilchytska, V., Berger, G., & Flandre, D. (2009). Efficient Single Event Upset Simulations of a Tolerant PD SOI CMOS D Flip-Flop. Proceedings of RADECS′09, 10th European Conference on Radiation Effects on Components and Systems, 225-229.
Bulteel, O., Delamare, R., & Flandre, D. (2009). High-efficiency solar cell embedded in SOI substrate for ULP autonomous circuits. Proceedings of the 2009 IEEE International SOI Conference, 2. https://doi.org/10.1109/SOI.2009.5318789
Burignat, S., Flandre, D., Kilchytska, V., Andrieu, F., Faynot, O., & Raskin, J.-P. (2009). Substrate Effects in sub-32 nm ultra thin SOI MOSFETs with thin buried oxide. Proceedings of the EUROSOI Conference. Published. EUROSOI Conference 2009, Göteborg (Sweden).
de Souza, M., Flandre, D., & Pavanello, M. A. (2009). Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures. Cryogenics, 49(11), 599-604. https://doi.org/10.1016/j.cryogenics.2008.12.010 (Original work published 2009)
Boulkenafet, H., Kezai, T., Gérard, P., & Flandre, D. (2009). Networking Strategies for Structural Health Monitoring with Autonomous Sensors. Proceedings of the CANEUS Workshop, International Collaborative Aerospace Development of Micro Nanotechnologies: From Concepts to Systems. CANEUS Workshop, International Collaborative Aerospace Development of Micro Nanotechnologies: From Concepts to Systems, NASA Ames Research Center (California/USA).
Gosset, G., Pollissard, G., & Flandre, D. (2009). Comparaison des performances de différentes architectures classiques d’OTA à très faible consommation dimensionnés à l’aide d’un outil original de CAO. Proceedings de FTFC′09, 8èmes journées d’études Faible Tension Faible Consommation. 8èmes journées d’études Faible Tension Faible Consommation (FTFC 2009), Neuchâtel/Suisse.
Bol, D., Kamel, D., Flandre, D., & Legat, J.-D. (2009). Nanometer MOSFET Effects on the Minimum-Energy Point of 45nm Subthreshold Logic. Proceedings of ISLPED′09, the IEEE/ACM International Symposium on Low-Power Electronics and Design (pp 3-8), San Francisco (California/USA).
Rue, B., André, N., Olbrechts, B., Gosset, G., Raskin, J.-P., & Flandre, D. (2009). High Temperature SOI CMOS Low Power circuits and micro systems for MEMS co-integrated interfaces, temperature sensing and power management applications. Proceedings of the International Collaborative Aerospace Development Micro Natnotechnologies: From concepts to systems – CANEUS 2009, p. Panel Session P10: Low TRL Devices (Sensors and Instrumentation).
Alvarado Pulido, J. J., Kilchytska, V., & Flandre, D. (2009). Assessment of advanced SOI technologies for high-temperature applications. Proceedings of the 8th Edition of the Diagnostics and Yield Symposium. 8th Edition of the Diagnostics and Yield Symposium, Warsaw (Poland).
Roda Neve, C., Kilchytska, V., Alvarado, J., Lederer, D., Militaru, O., Flandre, D., & Raskin, J.-P. (2009). Impact of neutron irradiation on oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer. Proceedings of the 10th edition the European Conference on Radiation and its Effects on Components and Systems - RADECS 2009, Paper A-6.
de Souza, M., Rue, B., Flandre, D., & Pavanello, M. A. (2009). Thermal sensing performance of lateral SOI PIN diodes in the 90-400 K range. Proceedings of the 2009 IEEE International SOI Conference, 2. https://doi.org/10.1109/SOI.2009.5318770
Gosset, G., & Flandre, D. (2009). A very high efficiency ultra-low-power 13.56MHz voltage rectifier in 150nm SOI CMOS. Proceedings of the 2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2009), 347-350. https://doi.org/10.1109/RFIT.2009.5383691
André, N., Gérard, P., Drochmans, P., Kezai, T., Druart, S., Moreno Hagelsieb, L., Francis, L., Flandre, D., & Raskin, J.-P. (2009). Wireless microsensors system for monitoring breathing activity. In Vander Sloten J., Nyssen M., Verdonck P., Haueisen, J. (Eds.) (ed.), Proceedings of the 4th European Conference of the International Federation for Medical and Biological Engineering (ECIFMBE 2008) (pp. 875-879). Springer verlag. https://doi.org/10.1007/978-3-540-89208-3_209
Druart, S., Pampin, R., Moreno Hagelsieb, L., Francis, L., & Flandre, D. (2009). Fluid characterization by interdigitated electrodes sensors. In Vander Sloten, J.; Nyssen, M.; Verdonck, P.; Haueisen, J.; (ed.), Proceedings of the 4th European Conference of the International Federation for Medical and Biological Engineering - ECIFMBE 2008 (pp. 2396-2399). Springer verlag. https://doi.org/10.1007/978-3-540-89208-3_575
Tang, X., Raskin, J.-P., Jonas, A., Nysten, B., Demoustier, S., Bayot, V., Francis, L., Pampin, R., Moreno Hagelsieb, L., & Flandre, D. (2009). Fabrication of SOI-based nano-biosensors. Proceedings of the 35th International Conference on Micro & Nano Engineering (MNE). Published. 35th International Conference on Micro & Nano Engineering (MNE), Ghent (Belgium).
Moreno Hagelsieb, L., André, N., Gérard, P., Kezai, T., Nizet, Y., Tang, X., Bulteel, O., Francis, L., Raskin, J.-P., & Flandre, D. (2009). Aluminium Oxide Based Sensors for Medical Applications. Proceedings of the 14th Biodetection Technologies Conference. Published. 14th Biodetection Technologies Conference, Baltimore (MD/USA).
Kamel, D., Standaert, F.-X., & Flandre, D. (2009). Scaling trends of the AES S-box low power consumption in 130 and 65 nm CMOS technology nodes. 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009, p. 1385-1388. https://doi.org/10.1109/ISCAS.2009.5118023
Ferreira, F. A. L. P., Pavanello, M. A., Cerdeira, A., & Flandre, D. (2009). Analytical Modeling of Double Gate Graded-Channel SOI Transistors for Analog Applications. Electrochemical Society. Proceedings, 139-144. (Original work published 2009)
Bawedin, M., Cristoloveanu, S., Flandre, D., & Udrea, F. (2009). Floating-Body Memory: Concepts, Physics and Challenges. Proceedings of the International Symposium on Silicon on Insulator Technology and Devices. International Symposium on Silicon on Insulator Technology and Devices, San Francisco (USA).
Kamel, D., Dessouky, M., & Flandre, D. (2009). Enhanced performance of SERDES current-mode output driver using 0.13 µm PD SOI CMOS. Proceedings of the IEEE Internationa SOI Conference 2009. IEEE Internationa SOI Conference 2009, California (USA).
Bawedin, M., Cristoloveanu, S., Udrea, F., & Flandre, D. (2009). Dynamic body potential variation in SOI MOSFETs: Physics, model and applications. Proceedings of the EUROSOI Conference 2009. EUROSOI Conference 2009, Göteborg (Sweden).
Bol, D., Legat, J.-D., De Vos, J., & Flandre, D. (2009). Ultra-low-power high-noise-margin logic with undoped FD SOI devices. 2009 IEEE International SOI Conference, 97-98. https://doi.org/10.1109/SOI.2009.5318760
Al Kadi Jazairli, M., & Flandre, D. (2009). Low power pulse generator as a capacitive interface for MEMS applications. Proceedings of the 2009 Ph.D. Research in Microelectronics and Electronics (PRIME), 312-315. https://doi.org/10.1109/RME.2009.5201366
Alvarado, J. J., Kilchytska, V., Militaru, O., Berger, G., & Flandre, D. (2009). The Effects of Neutron Irradiation on Analog Performance of Fully Depleted SOI MOSFETs. Proceedings of the EUROSOI Conference 2009. EUROSOI Conference 2009, Göteborg (Sweden).
Rue, B., Olbrechts, B., André, N., Raskin, J.-P., & Flandre, D. (2009). High temperature SOI CMOS low power circuits for MEMS co-integrated interfaces. Proceedings of hte International Conference and Exhibition on High Temperature Electronics Network – HiTEN 2009, Session 4, paper 2.
Burignat, S., Arshad, M. K. M., Raskin, J.-P., Kilchytska, V., Flandre, D., Faynot, O., Scheiblin, P., & Andrieu, F. (2009). Drain/substrate coupling impact on DIBL of ultra thin body and BOX SOI MOSFETs with undoped channel. In Tsoukalas, D.; Dimoulas, A.; (ed.), Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009 (pp. 141-144). IEEE. https://doi.org/10.1109/ESSDERC.2009.5331323
Kilchytska, V., & Flandre, D. (2009). Assessment of advanced SOI CMOS technologies for high-temperature applications. MUSICS Graduate School on Multimedia, Silicon, Communications, Louvain-la-Neuve (Belgium).
Alvarado Pulido, J. J., Kilchytska, V., & Flandre, D. (2009). Characterization and Modeling of Single Event transients in LDMOS-SOI technology. Proceedings of the MOS-AK/ESSDERC/ESSCIRC Workshop 2009. MOS-AK/ESSDERC/ESSCIRC Workshop 2009, Athens (Greece).
Bol, D., Flandre, D., & Legat, J.-D. (2009). Technology Flavor Selection and Adaptive Techniques for Timing-Constrained 45nm Subthreshold Circuits. Proceedings of ISLPED 2009, the IEEE/ACM International Symposium on Low-Power Electronics and Design (pp21-26), Millbrae (California/USA).
Pampin, R., & Flandre, D. (2009). Bio-compatible Insulated Substrate Impedance Transducers. In Vander Sloten, J.; Nyssen, M.; Verdonck, P.; Haueisen, J.; (ed.), Proceedings of the 4th European Conference of the International Federation for Medical and Biological Engineering - ECIFMBE 2008 (pp. 1180-1183). Springer verlag. https://doi.org/10.1007/978-3-540-89208-3_282
Boulkenafet, H., Kezai, T., Gérard, P., Lallart, M., Richard, C., & Flandre, D. (2009). Communication and Networking Strategies for Autonomous Actuators and Sensors. Proceedings of SMART′09, the IV ECCOMAS Thematic Conference on Smart Structures and Materials. IV ECCOMAS Thematic Conference on Smart Structures and Materials (SMART′09), Porto (Portugal).
Martin, E., Cortina Gil, E., Yee, L. S., Renaux, C., & Flandre, D. (2009). TRAPPIST/sub e/ pixel sensor with 2 mu m SOI technology. In Bo Yu; (ed.), 2009 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2009) (p. p. 1692-1695). IEEE. https://doi.org/10.1109/NSSMIC.2009.5402237
Rue, B., Olbrechts, B., André, N., Raskin, J.-P., & Flandre, D. (2009). High temperature SOI CMOS ultra low power circuits for MEMS co-integrated interfaces. Proceedings of the International Conference and Exhibition on HPigh Temperature Electronics Network - HiTEN 2009. Published. International Conference and Exhibition on High Temperature Electronics Network (HiTEN 2009), Oxford (United Kingdom).
Alvarado, J., Kilchytska, V., Flandre, D., Conde, J., Estrada, M., & Cerdeira, A. (2009). Continuous compact model for MuGFETs simulations. Proccedings of MIXDES 2009-16th International Conference Mixed Design of Integrated Circuits & Systems (MIXDES), 45-50.
Martin, M.-E., Soung Yee, L., Cortina, E., Renaux, C., & Flandre, D. (2009). Radiation Hard Pixel Sensor with SOI technology. Proceedings of IWoRID′09, 11th International Workshop on Radiation Imaging Detectors, p. II-61.
Alvarado, J. J., & Flandre, D. (2009). Device level support for emerging CMOS technologies. Proceedings of the MIXDES′09 Conference, special session on compact modeling, 31-32.
de Souza, M., Rue, B., Flandre, D., & Pavanello, M. A. (2009). On the Performance of Thin-Film Lateral SOI PIN Diodes as Thermal Sensors in a Wide Temperature Range. Proceedings of SBMicro′09, 24th Symposium on Microelectronics Technology and Devices, p. 397-404.
Rudenko, T., Kilchytska, V., Burignat, S., Raskin, J.-P., Andrieu, F., Faynot, O., Le Tiec, Y., Landry, K., Nazarov, A., Lysenko, V. S., & Flandre, D. (2009). Transconductance and mobility behaviors in UTB SOI MOSFETs with standard and thin BOX. Proceedings of the EUROSOI Conference 2009. Published. EUROSOI Conference 2009, Göteborg (Sweden).
Moreno Hagelsieb, L., André, N., Scheen, G., Gérard, P., Nizet, Y., Tang, X., Bulteel, O., Dupuis, P., Francis, L., Raskin, J.-P., & Flandre, D. (2009). Integration of aluminum oxide based sensors for medical and health monitoring applications. Proceedings of the 14th Annual Conference on Commercializing Micro- and Nanotechnology – COMS 2009. Published. The 14th Annual Conference on Commercializing Micro- and Nanotechnology – COMS 2009, Copenhagen (Denmark).
Moreno Hagelsieb, L., Nizet, Y., Tang, X., Raskin, J.-P., Flandre, D., & Francis, L. (2009). CMOS compatible anodic Al2O3 based sensors for bacteria detection. Procedia Chemistry, 1(1), 1283-1286. https://doi.org/10.1016/j.proche.2009.07.320 (Original work published 2009)
Moreno Hagelsieb, L., André, N., Scheen, G., Gérard, P., Nizet, Y., Tang, X., Bulteel, O., Dupuis, P., Francis, L., Flandre, D., & Raskin, J.-P. (2009). Aluminium Oxide Based Sensors Integration for Medical and Health Monitoring Applications. Proceedings of COMS′09, 14th Annual Conference on Commercializing Micro- and Nanotechnology. Published. 14th Annual Conference on Commercializing Micro- and Nanotechnology (COMS 2009), Copenhagen (Denmark).
Article de journal
Moreno Hagelsieb, L., Flandre, D., & Raskin, J.-P. (2009). Mechanical properties of anodic aluminum oxide for MEMS applications. Journal of Vacuum Science and Technology. Part B. Microelectronics and Nanometer Structures, 27(1), 542-546. https://doi.org/10.1116/1.3025906 (Original work published 2009)
Alvarado Pulido, J. J., Iniguez, B., Estrada, M., Flandre, D., & Cerdeira, A. (2009). Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation. International Journal of Numerical Modelling: Electronic Netwoks, Devices and Fields, 23, 88-106. https://doi.org/10.1002/jnm.725 (Original work published 2009)
Bol, D., Ambroise, R., Flandre, D., & Legat, J.-D. (2009). Interests and Limitations of Technology Scaling for Subthreshold Logic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(10), 1508-1519. https://doi.org/10.1109/TVLSI.2008.2005413 (Original work published 2009)
Moreno-Hagelsieb, L., Nizet, Y., Tang, X., Raskin, J.-P., Flandre, D., & Francis, L. (2009). CMOS compatible anodic Al2O3 based sensors for bacteria detection. Procedia Chemistry, 1, 1283-1286. (Original work published 2009)
Tang, X., Jonas, A., Nysten, B., Demoustier, S., Blondeau, F., Prévot, P.-P., Pampin, R., Godfroid, E., Iñiguez, B., Colinge, J.-P., Raskin, J.-P., Flandre, D., & Bayot, V. (2009). Direct protein detection with a nano-interdigitated array gate MOSFET. Biosensors and Bioelectronics, 24(12), 3531-3537. https://doi.org/10.1016/j.bios.2009.05.012 (Original work published 2009)
Tang, X., Bayot, V., Reckinger, N., Flandre, D., Raskin, J.-P., Dubois, E., & Nysten, B. (2009). A Simple Method for Measuring Si-Fin Sidewall Roughness by AFM. IEEE Transactions on Nanotechnology, 8(5), 611-616. https://doi.org/10.1109/TNANO.2009.2021064 (Original work published 2009)
Tang, X., Flandre, D., Reckinger, N., Bayot, V., Dubois, E., Yarekha, D. A., Larrieu, G., Lecestre, A., Ratajczak, J., Breil, N., Passi, V., & Raskin, J.-P. (2009). An electrical evaluation method for the silicidation of silicon nanowires. Applied Physics Letters, 95(2). https://doi.org/10.1063/1.3171929 (Original work published 2009)
Brevet
Pampin, R., Flandre, D., Moreno Hagelsieb, L., Foultier, B., & Remacle, J. (2009). Insulated substrate impedance transducers.
Papier de conférence
Gosset, G., Rue, B., & Flandre, D. (2008). Very high efficiency 13.56 MHz RFID input stage voltage multipliers based on ultra low power MOS diodes. Proceedings of the 2008 IEEE International Conference on RFID, 134-140.
de Souza, M., Flandre, D., & Pavanello, M. A. (2008). Channel Length Influence on the Performance of Source-Follower Buffers Implemented with Graded-Channel SOI nMOSFETs. Proceedings of the 23rd Symposium on Microelectronics Technology and Devices (SBMicro 2008), 263-272.
Roda Neve, C., Bol, D., Ambroise, R., Flandre, D., & Raskin, J.-P. (2008). Comparison of Digital Substrate Noise in SOI and Bulk Si CMOS Technologies. 7th Workshop on Low-Voltage Low Power Design, Louvain-la-Neuve (Belgium).
Bol, D., Ambroise, R., Flandre, D., & Legat, J.-D. (2008). Sub-45nm Fully-Depleted SOI CMOS Subthreshold Logic for Ultra-Low-Power Applications. Proceeding of the IEEE International SOI Conference 2008, p. 57 - 58.
El Oualkadi, A., & Flandre, D. (2008). Systematic HDL design of a Sigma - Delta fractional-N phase-locked loop for wireless applications. Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI, 173-178. https://doi.org/10.1109/ISVLSI.2008.40
André, N., Sobieski, S., Renaux, C., Flandre, D., & Raskin, J.-P. (2008). 3-D CMOS compatible MEMS sensors and actuators. proceedings of the Workshop on MEMS and Nanotechnology through Science and Applications. Published. Workshop on MEMS and Nanotechnology through Science and Applications, UCL/Louvain-la-Neuve (Belgium).
Doria, R. T., Cerdeira, A., Raskin, J.-P., Flandre, D., & Pavanello, M. A. (2008). Linearity Analysis in Double Gate Graded-Channel SOI Devices Applied to 2-MOS MOSFET-C Balanced Structures. Proceedings of SBMICRO 2008, the 23rd Symposium on Microelectronics Technology and Devices, 273-282.
Kezai, T., André, N., Gérard, P., Drochmans, P., Druart, S., Moreno Hagelsieb, L., Flandre, D., & Raskin, J.-P. (2008). Wireless Sensor Network For Breathing Activity Monitoring. Proceedings of the SR05 Satellite Conference - Topics in Electrical Circuits and Systems. Published. SR05 Satellite Conference - Topics in Electrical Circuits and Systems, Fez (Marocco).
Iniguez, B., & Flandre, D. (2008). Compact Modeling Techniques in Thin-Film SOI MOSFETs. Proceedings of the MOS Modeling and Parameter Extraction ESSDERC/ESSCIRC Workshop. MOS Modeling and Parameter Extraction ESSDERC/ESSCIRC Workshop, Edinburgh (UK).
Roda Neve, C., Bol, D., Ambroise, R., Flandre, D., & Raskin, J.-P. (2008). Digital substrate noise reduction by low-power circuit operation and SOI technology. Proceedings des 7e journées d’étude Faible Tension Faible Consommation, FTFC 2008, 23-28.
Moreno Hagelsieb, L., Flandre, D., & Raskin, J.-P. (2008). Anodic Aluminium Oxide Properties and its Interest for MEMS and DNA Sensors. Proceedings of the Regional Electrochemistry Meeting of South-east Asia. Published. Regional Electrochemistry Meeting of South-east Asia, Singapore.
Stamatakis, J., Gérard, P., Drochmans, P., Kezai, T., Caby, B., Macq, B., & Flandre, D. (2008). Study and Implementation of a wireless accelerometer network for gait analysis. Proceedings of the European Congress for medical and biomedical engineering, 2073-2076.
Moreno Hagelsieb, L., Flandre, D., & Raskin, J.-P. (2008). Mechanical properties of anodic aluminum oxide for microelectromechanical system applications. Journal of Vacuum Science and Technology. Part B. Microelectronics and Nanometer Structures, 27(1), 542-546. https://doi.org/10.1116/1.3025906 (Original work published 2009)
Bulteel, O., Dupuis, P., Jeumont, S., Irenge, L. M., Ambroise, J., Macq, B., Gala, J.-L., & Flandre, D. (2008). Low-cost miniaturized UV photosensor for direct measurement of DNA concentration within a closed tube container. In Vander Sloten, J.; Nyssen, M.; Verdonck, P.; Haueisen, J.; (ed.), Proceedings of the 4th European Conference of the International Federation for Medical and Biological Engineering - ECIFMBE 2008 (pp. 1057-1061). Springer verlag.
De Vos, J., Bol, D., & Flandre, D. (2008). Cellule SRAM 12 transistors à ultra faible courant de fuite. Proceedings des 7e journées d’étude Faible Tension Faible Consommation, FTFC 2008. 7e journées d’étude Faible Tension Faible Consommation, FTFC 2008, Louvain-la-Neuve/Belgique.
Flandre, D. (2008). SOI CMOS Devices and Circuits for High Temperature Electronics. Proceedings of the IEEE International SOI Conference : Short Course on Extreme SOI - Technology, Applications. IEEE International SOI Conference : Short Course on Extreme SOI - Technology, Applications, New Paltz, New York (USA).
Flandre, D. (2008). SOI for analog, digital and RF SOCs and microsystems applications.
Bol, D., & Flandre, D. (2008). Technology scaling for ultra-low-power circuits – Is mainstream technology adapted to special design? Ultimate Integration of Silicon Conference (ULIS), Udine (Italy).
Stamatakis, J., Gérard, P., Drochmans, P., Kezai, T., Caby, B., Macq, B., & Flandre, D. (2008). Study and implementation of a wireless accelerometer network for gait analysis. In Vander Sloten, J.; Nyssen, M.; Verdonck, P.; Haueisen, J.; (ed.), 4th European Conference of the International Federation for Medical and Biological Engineering - ECIFMBE 2008 (pp. 2073-2076). Springer verlag.
Bol, D., Legat, J.-D., Ambroise, R., & Flandre, D. (2008). Impact of technology scaling on digital subthreshold circuits. Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI, 179-184. https://doi.org/10.1109/ISVLSI.2008.75
Olbrechts, B., Rue, B., Flandre, D., & Raskin, J.-P. (2008). Cross-sensitivities of ring oscillators on thin dielectric membrane for pressure sensing applications. Proceedings of the EUROSOI - 2008, Fourth Workshop of the Thematic Network on Sil. Published. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2008), Tyndall National Institute, Cork, Ireland.
Bol, D., Flandre, D., & Legat, J.-D. (2008). Ultra-Low-Power logic style for low-frequency high-temperature applications. EUROSOI 2008 - Fourth workshop of the thematic network on silicon-on-insulator technology, devices and circuits, Cork (Ireland).
Kamel, D., Bol, D., & Flandre, D. (2008). Impact of layout style and parasitic capacitances in full adder. Proceedings of the 2008 IEEE International SOI Conference, 97-98. https://doi.org/10.1109/SOI.2008.4656312
Moreno Hagelsieb, L., André, N., Kezai, T., Bulteel, O., Druart, S., Pampin, R., Rue, B., Olbrechts, B., Raskin, J.-P., & Flandre, D. (2008). SOI Sensors Advantages for Consumer and Health Monitoring Applications. Proceedings of the Commercialization of Micro and Nano Systems Conference. Published. Commercialization of Micro and Nano Systems Conference, Mexico.
de Souza, M., Flandre, D., & Pavanello, M. A. (2008). Low Temperature and Channel Engineering Influence on the Behavior of Analog Source-Follower Buffers. Proceedings of the 8th International Workshop on Low Temperature Electronics. 8th International Workshop on Low Temperature Electronics (WOLTE 8), Jena (Germany).
André, N., Rue, B., Renaux, C., Flandre, D., & Raskin, J.-P. (2008). 3-D capacitive MEMS sensors co-integrated with SOI CMOS circuits. Proceedings of the EUROSOI - 2008, Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits, 75-76.
Bol, D., Ambroise, R., Flandre, D., & Legat, J.-D. (2008). Channel Length Upsize for Robust and Compact Subthreshold SRAM. Proceedings des 7e journées d’étude Faible Tension Faible Consommation, FTFC 2008, 117-120.
Colinge, J.-P., & Flandre, D. (2008). SOI Devices. IEEE International SOI conference: SOI Fundamentals Class, New Paltz, New York (USA).
Rue, B., & Flandre, D. (2008). A low-power and low-noise biopotential preamplifier in SOI CMOS technology. Proceedings of the European congress for medical and biomedical engineering. European congress for medical and biomedical engineering, Antwerp/Belgium.
Olbrechts, B., Rue, B., Flandre, D., & Raskin, J.-P. (2008). Cross-Sensitivities of Ring Oscillators on Thin Dielectric Membrane for Pressure Sensing Applications. Proceedings of the EUROSOI Conference, 73-74.
Flandre, D. (2008). A methodology to simulate soft error transients from technology to circuits in bulk and SOI CMOS. Topical day on “Radiation Tolerance: Instrumentation : from Transistor to Integrated Circuit”, SCK-CEN, Mol (Belgium).
André, N., Gérard, P., Drochmans, P., Kezai, T., Druart, S., Moreno-Hagelsieb, L., Flandre, D., & Raskin, J.-P. (2008). Wireless microsensors system for monitoring breathing activity. European Medical and Biological Engineering Congress – Engineering for Health – EMBEC’08, Antwerp (Belgium).
Bulteel, O., Dupuis, P., Jeumont, S., IRENGE, L. M., Gala, J. L., & Flandre, D. (2008). Direct Measurement of DNA Concentration within a closed tube container by UV light transmission and lateral p-i-n photodiode read-out in SOI technology. Proceedings of the fourth focused workshop on electronic recognition of bio-molecules. Fourth focused workshop on electronic recognition of bio-molecules, Liège (Belgium).
Bol, D., Legat, J.-D., Ambroise, R., & Flandre, D. (2008). Sub-45 nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications. Proceedings of the 2008 IEEE International SOI Conference, 57-58. https://doi.org/10.1109/SOI.2008.4656292
Flandre, D. (2008). Novel ultra low-power design techniques for analog, digital and memory functions - Implementations in SOI technology. 7th edition of Faible Tension Faible Consommation (FTFC 2008), Louvain-la-Neuve (Belgium).
de Souza, M., Flandre, D., & Pavanello, M. A. (2008). Improved Source-Follower Buffer Implementation by Using Graded-Channel SOI nMOSFETs. Proceedings of the EUROSOI - 2008, Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2008), Tyndall National Institute, Cork (Ireland).
Moreno Hagelsieb, L., Pampin, R., Bulteel, O., Olbrechts, B., André, N., Rue, B., Raskin, J.-P., & Flandre, D. (2008). Development of Micro- and Nano- Bio- and Environmental SOI-Sensors. Proceedings of the Workshop on MEMS and Nanotechnology through Science and Applications. Published. Workshop on MEMS and Nanotechnology through Science and Applications, UCL/Louvain-la-Neuve (Belgium).
Flandre, D. (2008). DNA electrical detection experiments with alumina passivated CMOS sensors. Cell Physiology and Biosensors Workshop, University Hasselt (Belgium).
Bol, D., & Flandre, D. (2008). Ultra-Low Power circuit design. First FDSOI tutorial of the Thematic Network on Silicon on Insulator technology, devices and circuits. First FDSOI tutorial of the Thematic Network on Silicon on Insulator technology, devices and circuits, Grenoble (France).
André, N., Rue, B., Renaux, C., Raskin, J.-P., & Flandre, D. (2008). Artificial microbeams to sense air flow, temperature or humidity combining MEMS and CMOS technologies. Sensors and Sensing in Biology and Engineering Conference, October 12 – 16, 2008, Cetraro (Italy).
André, N., Rue, B., Raskin, J.-P., & Flandre, D. (2008). Artificial microbeams to sense air flow and temperature combining MEMS and CMOS technologies. Proceedings of the ), Sensors and Sensing in Biology and Engineering, p. 50.
Rudenko, R., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2008). Evidence for Substrate Bias effects in SOI ΩFETs. Proceedings of the 2008 EUROSOI Conference, 137-138.
Bol, D., Ambroise, R., Flandre, D., & Legat, J.-D. (2008). Analysis and Minimization of Practical Energy in 45nm Subthreshold Logic Circuits. Proceedings of the IEEE International Conference on Computer Design, ICCD 2008, 294-300.
Flandre, D. (2008). Nouveaux concepts de fonctions mixtes à ultra-basse-consommation et température étendue en technologie CMOS SOI multi-tensions de seuil. Proceedings de l’Ecole d’hiver Francophone sur les Technologies de Conception des systèmes embarqués Hétérogènes (FETCH 2008). Ecole d’hiver Francophone sur les Technologies de Conception des systèmes embarqués Hétérogènes (FETCH 2008), Montréal (Québec).
Article de journal
Bawedin, M., Cristoloveanu, S., & Flandre, D. (2008). A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation. IEEE Electron Device Letters, 29(7), 795-798. https://doi.org/10.1109/LED.2008.2000601 (Original work published 2008)
Doria, R. T., Cerdeira, A., Raskin, J.-P., Flandre, D., & Pavanello, M. A. (2008). Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation. Microelectronics, 39(12), 1663-1670. https://doi.org/10.1016/j.mejo.2008.02.006 (Original work published 2008)
Tang, X., Reckinger, N., Larrieu, G., Dubois, E., Flandre, D., Raskin, J.-P., Nysten, B., Jonas, A., & Bayot, V. (2008). Characterization of ultrathin SOI film and application to short channel MOSFETs. Nanotechnology, 19(16), 165703. https://doi.org/10.1088/0957-4484/19/16/165703 (Original work published 2008)
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2008). Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities. IEEE Transactions on Electron Devices, 55(12), 3532-3541. https://doi.org/10.1109/TED.2008.2006776 (Original work published 2008)
Serban, D. A., Flandre, D., Kilchytska, V., Vlad, A., Martin-Hoyas, A., Nysten, B., Jonas, A., Geerts, Y. H., Lazzaroni, R., Bayot, V., & Melinte, S. (2008). Low-power dihexylquaterthiophene-based thin film transistors for analog applications. Applied Physics Letters, 92(14), 143503. https://doi.org/10.1063/1.2904963 (Original work published 2008)
de Souza, M., Flandre, D., & Pavanello, M. A. (2008). Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer. Solid-State Electronics, 52(12), 1933-1938. https://doi.org/10.1016/j.sse.2008.06.047 (Original work published 2008)
Bol, D., De Vos, J., Ambroise, R., Flandre, D., & Legat, J.-D. (2008). Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology. Solid-State Electronics, 52(12), 1939-1945. https://doi.org/10.1016/j.sse.2008.06.045 (Original work published 2008)
de Souza, M., Flandre, D., & Pavanello, M. (2008). Study of Matching Properties of Graded-Channel SOI MOSFETs. Journal of Integrated Circuits and Systems, 3(2), 69-75. (Original work published 2008)
Kilchytska, V., Flandre, D., & Raskin, J.-P. (2008). Silicon-on-Nothing MOSFETs: An efficient solution for parasitic substrate coupling suppression in SOI devices. Applied Surface Science, 254(19), 6168-6173. https://doi.org/10.1016/j.apsusc.2008.02.171 (Original work published 2008)
Doria, R. T., Cerdeira, A., Raskin, J.-P., Flandre, D., & Pavanello, M. A. (2008). Linearity analysis in Double Gate Graded-Channel SOI devices applied to 2-MOS MOSFET-C balanced structures. ECS Transactions, 14, 273-282. https://doi.org/10.1149/1.2956041 (Original work published 2008)
Balestra, F., Parker, E., Leadley, D. L., Mantl, S., Dubois, E., Engstrom, o., Clerc, R., Cristoloveanu, S., Kurz, H., Raskin, J.-P., Lemme, M., Ionescu, A., Kasper, E., Karmous, A., Baus, M., Spangenberg, B., Ostling, M., Sangiorgi, E., Ghibaudo, G., & Flandre, D. (2008). NANOSIL network of excellence-silicon-based nanostructures and nanodevices for long-term nanoelectronics applications. Materials Science in Semiconductor Processing, 11(5-6), 148-159. https://doi.org/10.1016/j.mssp.2008.09.017 (Original work published 2008)
Chapitre de livre
Kilchytska, V., Vancaillie, L., & Flandre, D. (2008). SOI Technology for Harsh Environment Applications. In Kobadze, Sergo B. (ed.), Solid State Electronics Research (pp. 185-215). Sergo B. Kobadze, Nova Publishers.
Papier de conférence
Kilchytska, V., & Flandre, D. (2007). Assessment of advanced SOI CMOS technologies for high-temperature applications. Proceedings of the International Conference on High Temperature Electronics (HITEN 2007). The International Conference on High Temperature Electronics (HITEN 2007), Oxford (Royaume-Uni).
Simoen, E., Flandre, D., Claeys, C., Chung, T. M., Pavanello, M. A., Martino, J. A., & Raskin, J.-P. (2007). The low-frequency noise behaviour of graded-channel SOI nMOSFETs. Solid-State Electronics, 51(2), 260-267. https://doi.org/10.1016/j.sse.2007.01.003 (Original work published 2007)
Bol, D., Legat, J.-D., Ambroise, R., & Flandre, D. (2007). Building ultra-low-power low-frequency digital circuits with high-speed devices. 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS ’07), p. 1404-1407.
Bawedin, M., Cristoloveanu, S., Dessard, V., & Flandre, D. (2007). Experiments and modeling of dynamic floating body effects in 1T-DRAM fully depleted SOI devices. In Napieralski, A. (ed.), Proceedings of the 14th International Conference Mixed Design of Integrated Circuits andSystems (pp. 84-88). IEEE.
Olbrechts, B., Rue, B., Rinaldi, G., Stiharu, I., Flandre, D., & Raskin, J.-P. (2007). SOI devices and ring oscillators on thin dielectric membranes for pressure sensing applications. Proccedings 2007 IEEE International SOI Conference, 109-110.
Bulteel, O., Afzalian, A., & Flandre, D. (2007). Conception d’un photocapteur à basses longueurs d’onde pour des mesures environnementales ou biomédicales. Proceedings of TAISA 2007, 8e Colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications. TAISA 2007, 8e Colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications, Lyon (France).
Santos, A., Pavanello, M. A., & Flandre, D. (2007). Impact of graded-channel SOI MOSFET application on the performance of cascode and wilson current mirrors. Proceedings of the 22nd Symposium on Microelectronics Technology and Devices (SBMicro 2007). 22nd Symposium on Microelectronics Technology and Devices (SBMicro 2007), Rio de janeiro (Brazil).
Kilchytska, V., Lederer, D., Flandre, D., & Raskin, J.-P. (2007). Substrate Parasitic Coupling in SOI Devices: Engineering Solutions. Proceedings of the 3rd International Workshop on New Group IV Semiconductor Nanoelectronics. Published. 3rd International Workshop on New Group IV Semiconductor Nanoelectronics, Tohoku University, Sendai (Japan).
Alvarado Pulido, J. J., Cerdeira, A., Kilchytska, V., & Flandre, D. (2007). Improved charge sheet model for PD SOI sub-micron MOSFETs. Proceedings of the 22nd Symposium on Microelectronics Technology and Devices (SBMicro 2007), 451-460.
Flandre, D. (2007). NANOTIC, Walloon programme of excellence at UCL. Proceedings of the Third International Nanotechnology Conference on Communication and Cooperation. Third International Nanotechnology Conference on Communication and Cooperation, Brussels (Belgium).
Santos, A., Pavanello, M. A., & Flandre, D. (2007). Improved charge sheet model for PD SOI sub-micron MOSFETs. Proceedings of the 22nd Symposium on Microelectronics Technology and Devices (SBMicro 2007). 22nd Symposium on Microelectronics Technology and Devices (SBMicro 2007), Rio de janeiro (Brazil).
Flandre, D. (2007). Small-signal Modelling of SOI-specific MOSFET Behaviours. Proceedings of MOS-AK/ESSDERC/ESSCIRC Workshop on Compact Modeling for Nano CMOS/SOI Technologies. MOS-AK/ESSDERC/ESSCIRC Workshop on Compact Modeling for Nano CMOS/SOI Technologies, Munich (Germany).
Kilchytska, V., Chung, T. M., Olbrechts, B., Vovk, Ya. N., Flandre, D., & Raskin, J.-P. (2007). On true Silicon-on-Insulator MOSFETs: fabrication by Si layer transfer over the pre-defined cavity and electrical characterization. Proceedings of the 5th International Symposium on Control of Semiconductor Interfaces for Next Generation ULSI Process Integrations - ISCSI-V. Published. 5th International Symposium on Control of Semiconductor Interfaces for Next Generation ULSI Process Integrations - ISCSI-V, Tokyo (Japan).
Olbrechts, B., André, N., Rue, B., Flandre, D., & Raskin, J.-P. (2007). SOI co-integrated microsensors. Proceedings of the 7th MEMUNITY - The MEMS Test Community - Workshop, Paper 10.
Kilchytska, V., Pailloncy, G., Raskin, J.-P., Collaert, N., Jurczak, M., & Flandre, D. (2007). Substrate-related output conductance frequency response of FD SOI MOSFETs: influence of channel length and substrate temperature. Proceedings of ULIS 2007, the 8th International Conference on Ultimate Integration on Silicon. Published. 8th International Conference on Ultimate Integration on Silicon (ULIS 2007), Leuven/Belgium.
Moreno Hagelsieb, L., Flandre, D., Foultier, B., Laurent, G., Pampin, R., Remacle, J.-F., & Raskin, J.-P. (2007). Electrical detection of DNA hybridization: Three extraction techniques based on interdigitated Al/Al2O3 capacitors. Biosensors and Bioelectronics, 22(9-10), 2199-2207. https://doi.org/10.1016/j.bios.2006.10.024 (Original work published 2007)
Flandre, D. (2007). SOI-specific MOSFET modeling issues. Proceedings of ULIS 2007 - Tutorial Session on Advanced Modeling. ULIS 2007 - Tutorial Session on Advanced Modeling, Leuven (Belgium).
Rue, B., & Flandre, D. (2007). A SOI CMOS Smart High-Temperature Sensor. Proceedings of the 2007 IEEE International SOI Conference. 2007 IEEE International SOI Conference.
Kilchytska, V., Flandre, D., Chung, T. M., Olbrechts, B., Vovk, Ya., & Raskin, J.-P. (2007). Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity. Solid-State Electronics, 51(9), 1238-1244. https://doi.org/10.1016/j.sse.2007.07.021 (Original work published 2007)
de Souza, M., Pavanello, M. A., & Flandre, D. (2007). Analysis of matching in graded-channel SOI MOSFETs. Proceedings of the 22nd Symposium on Microelectronics Technology and Devices (SBMicro 2007). 22nd Symposium on Microelectronics Technology and Devices (SBMicro 2007), Rio de janeiro (Brazil).
Kilchytska, V., Collaert, N., Jurczak, M., & Flandre, D. (2007). Multi-gate MOSFET behavior at high temperatures. Conference proceedings of EUROSOI 2007. EUROSOI 2007, Leuven (Belgium).
El Oualkadi, A., El Kaamouchi, M., Paillot, J.-M., Vanhoenacker-Janvier, D., & Flandre, D. (2007). Fully integrated high-Q switched capacitor bandpass filter with center frequency and bandwidth tuning. Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEECat No. 07CH37828C), 4. https://doi.org/10.1109/RFIC.2007.380974
Moreno Hagelsieb, L., Pampin, R., Druart, S., & Flandre, D. (2007). Al/Al2O3 Biosensors for DNA and Medical Applications: Materials and Design Concepts, Methodology and Perspectives. Proceedings of PRO-BIOSYS workshop, Micro-Nanotechnology for Biomedical Applications (Bio-chips). PRO-BIOSYS workshop, Micro-Nanotechnology for Biomedical Applications (Bio-chips), Bucharest (Romania).
Simoen, E., Claeys, C., Chung, T. M., Flandre, D., & Raskin, J.-P. (2007). The Length-Dependence of the 1/f Noise of Graded-Channel SOI nMOSFETs. Proceedings of the 22nd Symposium on Microelectronics Technology and Devices - SBMicro′2007, Session “Characterization and Modeling III”, paper # 2.
Moreno Hagelsieb, L., Pampin, R., Bulteel, O., Olbrechts, B., André, N., Rue, B., Raskin, J.-P., & Flandre, D. (2007). Development of New Micro- and Nano- Bio- and Environmental SOI-Sensors in UCL. Proceedings of the Scientific workshop: Microsystems as a Platform for Integrating Micro/Nano/Biotechnologies, Session III, paper 5.
Kilchytska, V., & Flandre, D. (2007). FinFETs perspectives for high-temperature applications. Proceedings of HITEN 2007. The International Conference on High Temperature Electronics (HITEN 2007), Oxford (United Kingdom).
Bol, D., Ambroise, R., Roda Neve, C., Raskin, J.-P., & Flandre, D. (2007). Wide-band simulation and characterization of digital substrate noise in SOI technology. Proccedings 2007 IEEE International SOI Conference, 133-134.
Pavanello, M. A., Cerdeira, A., Raskin, J.-P., & Flandre, D. (2007). Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures. Proceedings of the 211th Meeting of the Electrochemical Society – ECS’07, Paper 734.
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2007). Electrical properties of FinFET structures. Proceedings of the III Ukrainian Conference on Semiconductor Physics, 113.
Flandre, D. (2007). Ultra-low-power and high-temperature CMOS design techniques for analog, digital and memory functions. Implementations in SOI technology. Proceedings of the ENCASIT Workshop on Technologies for Harsh-Environment – From Semiconductors to a System. ENCASIT Workshop on Technologies for Harsh-Environment – From Semiconductors to a System, Vilvoorde (belgium).
Kilchytska, V., Chung, M., Vovk, Ya. N., Raskin, J.-P., & Flandre, D. (2007). True Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity. Proceedings of EUROSOI 2007, Third Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits. Published. Third Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2007), Leuven, Belgium.
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2007). Experimental Study of the Effective Mobility in Doped- and Undoped-Channel Triple-Gate FinFET Structures. Conference proceedings of EUROSOI 2007. EUROSOI 2007, Leuven (Belgium).
Article de journal
Gluszko, G., Lukasiak, L., Kilchytska, V., Chung, T. M., Olbrechts, B., Flandre, D., & Raskin, J.-P. (2007). Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities. Journal of Telecommunications and Information Technology, 3, 61-66. (Original work published 2007)
Yun, J.-G., Bawedin, M., Cristoloveanu, S., Flandre, D., & Lee, H.-D. (2007). The meta-stable dip (MSD) effect in SOI FinFETs. Microelectronic Engineering, 84(4), 590-593. https://doi.org/10.1016/j.mee.2006.11.012 (Original work published 2007)
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2007). Substrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs. IEEE Electron Device Letters, 28(9), 834-836. https://doi.org/10.1109/LED.2007.903955 (Original work published 2007)
Raskin, J.-P., Flandre, D., Iker, F., André, N., Olbrechts, B., & Pardoen, T. (2007). Bulk and surface micromachined MEMS in thin film SOI technology. Electrochimica Acta, 52(8), 2850-2861. https://doi.org/10.1016/j.electacta.2006.09.021 (Original work published 2007)
Afzalian, A., & Flandre, D. (2007). Characterization of quantum efficiency, effective lifetime and mobility in thin film ungated SOI lateral PIN photodiodes. Solid-State Electronics, 51(2), 337-342. https://doi.org/10.1016/j.sse.2007.01.009 (Original work published 2007)
Alvarado, J., Cerdeira, A., Kilchytska, V., & Flandre, D. (2007). Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs. Microelectronics, 38(3), 321-326. https://doi.org/10.1016/j.mejo.2007.01.017 (Original work published 2007)
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A. N., Lysenko, V. S., & Flandre, D. (2007). Electrical properties of FinFET structures. PHYSICAL SENSORS AND MICROSYSTEMS TECHNOLOGIES, 13-18. (Original work published 2007)
Rudenko, T., Flandre, D., Kilchytska, V., Collaert, N., Jurczak, M., & Nazarov, A. (2007). Reduction of gate-to-channel tunneling current in FinFET structures. Solid-State Electronics, 51(11-12), 1466-1472. https://doi.org/10.1016/j.sse.2007.09.016 (Original work published 2007)
Hassoune, I., Macé, F., Flandre, D., & Legat, J.-D. (2007). Dynamic differential self-timed logic families for robust and low-power security ICs. Integration : the V L S I journal, 40(3), 355-364. https://doi.org/10.1016/j.vlsi.2006.04.001 (Original work published 2007)
Bawedin, M., Flandre, D., & Cristoloveanu, S. (2007). Innovating SOI memory devices based on floating-body effects. Solid-State Electronics, 51(10), 1252-1262. https://doi.org/10.1016/j.sse.2007.06.024 (Original work published 2007)
Kilchytska, V., Pailloncy, G., Lederer, D., Raskin, J.-P., Collaert, N., Jurczak, M., & Flandre, D. (2007). On the substrate-related variation of the small-signal output conductance in advanced MOSFETs. IEEE Electron Device Letters, 419-421. (Original work published 2007)
El Hamid, H. A., Guitart, J. R., Kilchytska, V., Flandre, D., & Iniguez, B. (2007). A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs. IEEE Transactions on Electron Devices, 54(9), 2487-2496. https://doi.org/10.1109/TED.2007.902415 (Original work published 2007)
Doria, R. T., Pavanello, M. A., Cerdeira, A., Raskin, J.-P., & Flandre, D. (2007). Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures. Journal of the Electrochemical Society, 6(4), 217-222. (Original work published 2007)
Bol, D., Hassoune, I., Levacq, D., Flandre, D., & Legat, J.-D. (2007). Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. Journal of Multiple-Valued Logic and Soft Computing, 13(1-2), 61-77. (Original work published 2007)
Kilchytska, V., Pailloncy, G., Lederer, D., Raskin, J.-P., Collaert, N., Jurczak, M., & Flandre, D. (2007). Frequency variation of the small-signal output conductance of decananometer MOSFETs due to substrate crosstalk. IEEE Electron Device Letters, 28(5), 419-421. https://doi.org/10.1109/LED.2007.895374 (Original work published 2007)
Kilchytska, V., Flandre, D., Collaert, N., & Jurczak, M. (2007). Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures. Solid-State Electronics, 51(9), 1185-1193. https://doi.org/10.1016/j.sse.2007.07.020 (Original work published 2007)
Levacq, D., Dessard, V., & Flandre, D. (2007). Low leakage SOICMOS static memory cell with ultra-low power diode. IEEE Journal of Solid State Circuits, 42(3), 689-702. https://doi.org/10.1109/JSSC.2006.891494 (Original work published 2007)
Simoen, E., Claeys, C., Chung, T. M., Flandre, D., & Raskin, J.-P. (2007). The Length-Dependence of the 1/f Noise of Graded-Channel SOI nMOSFETs. ECS Transactions, 9(1), 373-381 (September). https://doi.org/10.1149/1.2766908 (Original work published 2007)
Kilchytska, V., Chung, T. M., Vovk, Y., Raskin, J.-P., & Flandre, D. (2007). True Silicon-on-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity. Solid-State Electronics, 51, 1238-1244. (Original work published 2007)
Chung, T. M., Olbrechts, B., Flandre, D., Södervall, U., Bengtsson, S., & Raskin, J.-P. (2007). Planar Double-Gate SOI MOS devices by wafer bonding over pre-patterned cavities. Solid-State Electronics, 51(2), 231-238. https://doi.org/10.1016/j.sse.2007.01.017 (Original work published 2007)
Moldovan, O., Cerdeira, A., Jimenez, D., Raskin, J.-P., Kilchytska, V., Flandre, D., Collaert, N., & Iniguez, B. (2007). Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications. Solid-State Electronics, 51(5), 655-661. https://doi.org/10.1016/j.sse.2007.02.039 (Original work published 2007)
Simoen, E., Flandre, D., Claeys, C., Chung, T. M., & Raskin, J.-P. (2007). On the origin of the excess low-frequency noise in graded-channel silicon-on-insulator nMOSFETs. IEEE Electron Device Letters, 28(10), 919-921. https://doi.org/10.1109/LED.2007.905958 (Original work published 2007)
Moreno Hagelsieb, L., Laurent, G., Pampin, R., Foultier, B., Remacle, J.-F., Raskin, J.-P., & Flandre, D. (2007). Electrical detection of DNA hybridization : three extraction techniques based on interdigitated Al/Al2O3 capacitors. Biosensors and Bioelectronics, 22(9-10), 2199-2207. (Original work published 2007)
Olbrechts, B., Rue, B., Suski, J., Flandre, D., & Raskin, J.-P. (2007). Characterization of FD SOI devices and VCO’s on ONO membranes under pressure. Solid-State Electronics, 51(9), 1229-1237. https://doi.org/10.1016/j.sse.2007.07.026 (Original work published 2007)
Simoen, E., Claeys, C., Chung, T. M., Flandre, D., Raskin, J.-P., Pavanello, M. A., & Martino, J. A. (2007). Low-frequency noise behavior of graded-channel SOI n-MOSFETs. Solid-State Electronics, 51(2), 260-267. (Original work published 2007)
Chapitre de livre
Kilchytska, V., Levacq, D., Lederer, D., Pailloncy, G., Raskin, J.-P., & Flandre, D. (2007). Substrate effect on the output conductance frequency response of SOI MOSFETs (inited paper). In S. Hall, A.N. Nazarov, V.S. Lysenko (eds) (ed.), Nanoscaled Semiconductor-on-Insulator Structures and Devices (pp. 221-238). Kluwer Academic Publishers.
Rudenko, T., Kilchytska, V., Collaert, N., Nazarov, A., Jurczak, M., & Flandre, D. (2007). Electrical characterization and special properties of FinFET structures. In Nanoscaled Semiconductor-on-Insulator Structures and Devices (pp. 199-220). S. Hall, A.N. Nazarov, V.S. Lysenko.
Papier de conférence
Akarvardar, K., Cristoloveanu, S., Bawedin, M., Gentil, P., Blalock, B., & Flandre, D. (2006). Fully Depleted Four-Gate Transistors. Eurosoi 2006 Conference Proceedings, 137-138.
Pampin, R., Foultier, B., Moreno Hagelsieb, L., Heusdens, B., Raskin, J.-P., Destine, J., Remacle, J.-F., & Flandre, D. (2006). Insulated substrate impedance transducers: an innovative semiconductor device applied to labelled DNA sensing. Proceedings of the Nanoelectronics days (ND). Published. Nanoelectronics days (ND), Aachen (Allemagne).
Afzalian, A., Torfs, T., Van hoof, C., & Flandre, D. (2006). Characterization of Quantum Efficiency and Effective Lifetime in Thin Ungated SOI Lateral PIN Photodiodes in the UV-Range. Eurosoi 2006 Conference Proceedings, 67-68.
Moldovan, O., Cerdeira, A., Jimenez, D., Raskin, J.-P., Kilchytska, V., Flandre, D., Collaert, N., & Iniguez, B. (2006). Compact Model of Double-Gate MOSFETs for Low Power Analog Applications. Proceedings of XXI Conference on Design of Circuits and integrated Systems (DCIS 2006). Published. XXI Conference on Design of Circuits and integrated Systems (DCIS 2006), Barcelona/Spain.
Pavanello, M. A., Cerdeira, A., Martino, J. A., Raskin, J.-P., & Flandre, D. (2006). Impact of Asymmetric Channel Configuration on the Linearity of Double-Gate SOI MOSFETs. Proceedings of the 6th International Caribbean Conference on Devices, Circuits and Systems, 187-192.
de Souza, M., Pavanello, M. A., Cerdeira, A., & Flandre, D. (2006). Graded-channel SOI nMOSFET model valid for harmonic distortion evaluation. Proceedings of the 25th International Conference on Microelectronics (MIEL 2006), 476-479.
Chung, T. M., Olbrechts, B., Flandre, D., Södervall, U., Bengtsson, S., & Raskin, J.-P. (2006). Planar Double-Gate SOI MOS devices by wafer bonding over pre-patterned cavities. Proceedings of the Second Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits – EuroSOI’05, pp. 111-112.
Moreno Hagelsieb, L., Foultier, B., Pampin, R., Raskin, J.-P., Remacle, J., & Flandre, D. (2006). Investigation of Al/Al2O3 interdigitated structures on Si biochips towards the elctrical detection of TP53 DNA single point mutations. Proceedings of ERBM3 Collonster, Third Focused Workshop on Electronic Recognition of Bio-molecules. Published. ERBM3 Collonster, Third Focused Workshop on Electronic Recognition of Bio-molecules, Liège (Belgium).
Kilchytska, V., Rudenko, T., & Flandre, D. (2006). Electrical characterization of FinFETs: Special aspects. Proceedings of the 7th Symposium Diagnostics & Yield: Advanced Silicon Devices and Technologies for ULSI Era. 7th Symposium Diagnostics & Yield: Advanced Silicon Devices and Technologies for ULSI Era, Warszawa (Poland).
Doria, R., Pavanello, M., Cerdeira, A., Raskin, J.-P., & Flandre, D. (2006). Channel Length Reduction Influence On Harmonic Distortion Of Graded-Channel Gate-All-Around Devices. Proceedings of the 21st Symposium on Microelectronics Technology and Devices - SBMicro2006, Paper B4.
Simoen, E., Claeys, C., Chung, T. M., Flandre, D., & Raskin, J.-P. (2006). Low-frequency noise behavior of graded-channel SOI n-MOSFETs. Second Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits – EuroSOI’06, Grenoble (France).
Cerdeira, A., Aleman, M., Kilchytska, V., Collaert, N., De Meyer, K., & Flandre, D. (2006). Nonlinearity Analysis of FinFETs. Proceedings of the 6th International Caribbean Conference on Devices, Circuits and Systems, 9-12.
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2006). Experimental evidence for reduction of gate tunneling current in FinFET structures and its dependence on the Fin width. Proceedings of the 36th European Solid-State Device Research Conference (ESSDERC 2006), 375-378.
Moreno Hagelsieb, L., Laurent, G., Pampin, R., Flandre, D., Raskin, J.-P., Foultier, B., & Remade, J.-F. (2006). On-chip RF detection of DNA hybridization based on interdigitated Al²O³ capacitors. In Ionescu, A.M.; Declercq, M.; Leblebici, Y.; (ed.), Proceedings of ESSDERC 2006. Proceedings of the 36th European Solid-State DeviceResearch Conference (IEEE Cat. No. 06EX1346) (pp. 125-128). IEEE.
de Souza, M., Pavanello, M. A., & Flandre, D. (2006). Submicrometer graded-channel SOI MOSFET modeling for low temperature analog circuit design. Proceedings of the Seventh International Workshop on Low Temperature Electronics, WOLTE-7. Seventh International Workshop on Low Temperature Electronics, WOLTE-7, Noordwijk (The Netherlands).
Bawedin, M., Cristoloveanu, S., & Flandre, D. (2006). Novel capacitor-less 1T-DRAM using MSD effect. IEEE Catalogue N°06CH37786, 109-110.
El Oualkadi, A., & Flandre, D. (2006). Synthèse d’une PLL N-fractionnaire avec VHDL-AMS pour systèmes de communication sans fil de type ZigBee. Proceedings du 7e colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications. 7e colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications, Strasbourg (France).
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2006). Electrical Characterisation and Special Properties of FinFET Structures. Abstracts of NATO Advanced Research Workshop “Nanoscaled Semiconductor-on-Insulator Structures and Devices. Published. NATO Advanced Research Workshop “Nanoscaled Semiconductor-on-Insulator Structures and Devices”, Sudak/Crimea (Ukrain).
Rue, B., Levacq, D., & Flandre, D. (2006). Low-voltage low-power high-temperature SOI CMOS rectifiers. IEEE Catalogue N°06CH37786, 65-66.
Moreno Hagelsieb, L., Laurent, G., Foultier, B., Pampin, R., Remacle, J.-F., Raskin, J.-P., & Flandre, D. (2006). DNA hybridization electrical detection by 3 independent measurement techniques based on interdigitated Al/Al2O3 capacitors. Proceedings of the Ninth World Congress on Biosensors 2006, 380.
Bol, D., Avedillo, M. J., Quintana, J., Flandre, D., & Legat, J.-D. (2006). Investigation of Monostable-Bistable Transition Logic Element Circuits based on Ultra-Low-Power Diodes. Eurosoi 2006 Second Workshop of the thematic Network on Silicon On Insulator Technology, Devices and Circuits, Grenoble (France).
Olbrechts, B., Flandre, D., & Raskin, J.-P. (2006). Thin-film SOI CMOS for heterogeneous microsystems. Proceedings of the CANEUS 2006 Conference – Micro-Nano Technologies for Aerospace Applications, 9 pages.
Afzalian, A., & Flandre, D. (2006). Speed performances of thin-film lateral SOI PIN photodiodes up to tens of GHz. Proceedings of the 2006 IEEE International SOI Conference, 83-84. https://doi.org/10.1109/SOI.2006.284444
Gluszko, G., Lukasiak, L., Kilchytska, V., Chung, T. M., Olbrechts, B., Flandre, D., & Raskin, J.-P. (2006). Charge pumping characterization of SOI PIN diodes. Journal of Telecommunications and Information Technology, 3, 61-66. (Original work published 2007)
Pampin, R., Moreno Hagelsieb, L., & Flandre, D. (2006). Investigation of Al/Al2O3 interdigitated structures on Si biochips towards the electrical detection of TP53 DNA single point mutations. Proceedings of the Third Focused Workshop on Electronic Recognition of Bio-Molecules – ERBM 3. Third Focused Workshop on Electronic Recognition of Bio-Molecules – ERBM 3, University of Liège (Belgium).
Alvarado, J. J., Cerdeira, A., Kilchytska, V., & Flandre, D. (2006). A Modified EKV PDSOI MOSFETs Model. Proceedings of the 25th International Conference on Microelectronics (MIEL 2006). 25th International Conference on Microelectronics (MIEL 2006), Belgrade (Serbia and Montenegro).
Jun, J.-G., Cristoloveanu, S., Bawedin, M., & Flandre, D. (2006). Meta-stable DIP (MSD) Effect in SOI FinFETs. Proceedings of the 13th Korean Conference on Semiconductors, 1197-1198.
Kilchytska, V., & Flandre, D. (2006). Substrate Effect on the output conductance frequency response of SOI MOSFETs. Proceedings of NATO Advanced Research Workshop “Nanoscaled Semiconductor-on-Insulator Structures and Devices”. NATO Advanced Research Workshop “Nanoscaled Semiconductor-on-Insulator Structures and Devices, Sudak/Crimea (Ukraine).
Pampin, R., Foultier, B., Moreno Hagelsieb, L., Heusdens, B., Raskin, J.-P., Destine, J., Remacle, J.-F., & Flandre, D. (2006). An ISFET-like innovative device applied to labeled DNA detection. Proceedings of the Third Focused Workshop on Electronic Recognition of Bio-Molecules – ERBM 3. Published. Third Focused Workshop on Electronic Recognition of Bio-Molecules – ERBM 3, University of Liège (Belgium).
Raskin, J.-P., Iker, F., Andre, N., Olbrecht, B., Fabregue, D., Bertholet, Y., Flandre, D., & Pardoen, T. (2006). Bulk and surface micromachined SOI MEMS: from sensors to testing micromachines. Proceedings of the 4th International Society of Electrochemistry (ISE) Spring Meeting 2006, p. 63.
Akarvardar, K., Cristoloveanu, S., Bawedin, M., Gentil, P., Blalock, B. J., & Flandre, D. (2006). Thin Film Fully-Depleted SOI Four-Gate Transistors. Solid-State Electronics, 51(2), 278-284. https://doi.org/10.1016/j.sse.2007.01.013 (Original work published 2006)
Houk, Y., Iniguez, B., Flandre, D., & Nazarov, A. (2006). Modeling of the AM SOI pMOSFETs. Eurosoi 2006 Conference Proceedings, 79-80.
Hasler, I., Buiu, O., Rue, B., & Flandre, D. (2006). Design of a Low Voltage-Low Power, Highly linear Fully-Depleted SOI Operational Transconductance Amplifier for Hearing Aid Application. Eurosoi Conference Proceedings, 27-28.
Article de journal
Afzalian, A., & Flandre, D. (2006). Monolithically integrated 10 Gbit/s photodiode and transimpedance amplifier in thin-film SOICMOS technology. Electronics Letters, 42(24), 1420-1421. https://doi.org/10.1049/el:20062563 (Original work published 2006)
Vancaillie, L., Flandre, D., Kilchytska, V., Alvarado, J., & Cerdeira, A. (2006). Characterization and design methodology for low-distortion MOSFET-C analog structure’s in multithreshold deep-submicrometer SOICMOS technologies. IEEE Transactions on Electron Devices, 53(2), 263-269. https://doi.org/10.1109/TED.2005.861725 (Original work published 2006)
Yun, J., Flandre, D., Cristoloveanu, S., Bawedin, M., & Lee, H. (2006). Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs. IEEE Electron Device Letters, 27(2), 123-126. https://doi.org/10.1109/LED.2005.862684 (Original work published 2006)
Sanz, M. T., Calvo, B., Celma, S., & Flandre, D. (2006). Self-cascode SOI versus graded-channel SOI MOS transistors. IEEE Proceedings-Circuits Devices and Circuits, 153(5), 461-465. https://doi.org/10.1049/ip-cds:20060058 (Original work published 2006)
Hassoune, I., Macé, F., Flandre, D., & Legat, J.-D. (2006). Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks. Microelectronics, 37(9), 997-1006. https://doi.org/10.1016/j.mejo.2006.01.020 (Original work published 2006)
Raskin, J.-P., Flandre, D., Chung, T., Kilchytska, V., & Lederer, D. (2006). Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization. IEEE Transactions on Electron Devices, 53(5), 1088-1095. https://doi.org/10.1109/TED.2006.871876 (Original work published 2006)
Houk, Y., Iniguez, B., Flandre, D., & Nazarov, A. (2006). C-infinity-continuous high-temperature model for low-doped accumulation mode silicon-on-insulator pMOSFETs. Solid-State Electronics, 50(7-8), 1261-1268. https://doi.org/10.1016/j.sse.2006.04.046 (Original work published 2006)
El Oualkadi, A., Paillot, J. M., & Flandre, D. (2006). Clock Jitter effect on switched-capacitor filter design. Fluctuation and Noise Letters : an interdisciplinary scientific journal on random processes in physical, biological and technological systems, 6(1), 29-33. https://doi.org/10.1142/S0219477506003112 (Original work published 2006)
Gimenez, S., Flandre, D., Pavanello, M., & Martino, J. (2006). Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS. Microelectronics Journal, 37(1), 31-37. https://doi.org/10.1016/j.mejo.2005.06.010 (Original work published 2006)
Doria, R. T., Pavanello, M. A., Cerdeira, A., Raskin, J.-P., & Flandre, D. (2006). Channel Length Reduction Influence on Harmonic Distortion of Graded-Channel Gate-All-Around Devices. Electrochemical Society. Transactions, 4(1), 247-256. https://doi.org/10.1149/1.2813497 (Original work published 2006)
Pavanello, M., Flandre, D., Der Agopian, P., & Martino, J. (2006). Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. Microelectronics, 37(2), 137-144. https://doi.org/10.1016/j.mejo.2005.04.046 (Original work published 2006)
Simoen, E., Claeys, C., Chung, T. M., Flandre, D., Pavanello, M. A., Martino, J. A., & Raskin, J.-P. (2006). Low-frequency noise behaviour of graded-channel SOI nMOSFETs. Solid-State Electronics, 51(2), 260-267. https://doi.org/10.1016/j.sse.2004.01.003 (Original work published 2007)
Chapitre de livre
Pampin, R., Foultier, B., Raskin, J.-P., Remacle, J., & Flandre, D. (2006). DNA Analytical CMOS Systems-on-a-Chip. In American Scientific Publishers (ed.), Encyclopedia of Sensors (p. p. 395-412). C.A.Grimes, E.C.Dickey, and M.V.Pishko.
Monographie
Laconte, J., Flandre, D., & Raskin, J.-P. (2006). Micromachined thin-film sensors for SOI-CMOS co-integration. Springer.
Article de journal
Kilchytska, V., Flandre, D., Lederer, D., Collaert, N., & Raskin, J.-P. (2005). Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: Suppression of the influence of floating-body effects. IEEE Electron Device Letters, 26(10), 749-751. https://doi.org/10.1109/LED.2005.855408 (Original work published 2005)
Kranti, A., Flandre, D., Chung, T., & Raskin, J.-P. (2005). Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs. Semiconductor Science and Technology, 20(5), 423-429. https://doi.org/10.1088/0268-1242/20/5/017 (Original work published 2005)
Pavanello, M. A., Flandre, D., Martino, J. A., & Raskin, J.-P. (2005). High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures. Solid-State Electronics, 49(10), 1569-1575. https://doi.org/10.1016/j.sse.2005.08.005 (Original work published 2005)
Eggermont, J.-P., Flandre, D., Raskin, J.-P., & Colinge, J.-P. (2005). Potential and modeling of 1-mM SOI CMOS operational transconductance amplifiers for applications up to 1 GHz. IEEE Journal of Solid State Circuits, 33(4), 640-646 (April). (Original work published 2005)
Hassoune, H., Flandre, D., Legat, J.-D., Drummond, A., Gaudissart, A., Bol, D., & Levacq, D. (2005). A new multi-valued current-mode adder based on negative-differential resistance using ULP diodes. Solid-State Electronics, 49(7), 1185-1191. https://doi.org/10.1016/j.sse.2005.05.004 (Original work published 2005)
Lederer, D., Flandre, D., & Raskin, J.-P. (2005). High frequency degradation of body-contacted PD SOI MOSFET output conductance. Semiconductor Science and Technology, 20(5), 469-472. https://doi.org/10.1088/0268-1242/20/5/025 (Original work published 2005)
Rudenko, T., Collaert, N., De Gendt, S., Kilchytska, V., Jurczak, M., & Flandre, D. (2005). Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode. Microelectronic Engineering, 80, 386-389. https://doi.org/10.1016/j.mee.2005.04.026 (Original work published 2005)
de Souza, M., Flandre, D., Pavanello, M., & Iniguez, B. (2005). A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation. Solid-State Electronics, 49(10), 1683-1692. https://doi.org/10.1016/j.sse.2005.08.001 (Original work published 2005)
Rudenko, T., Flandre, D., Kilchytska, V., & Dessard, V. (2005). A revised reverse gated-diode technique for determining generation parameters in thin-film silicon-on-insulator devices and its application at high temperatures. Journal of Applied Physics, 97(9), 9 pages. https://doi.org/10.1063/1.1893211 (Original work published 2005)
Afzalian, A., & Flandre, D. (2005). Physical modeling and design of thin-film SOI lateral PIN photodiodes. IEEE Transactions on Electron Devices, 52(6), 1116-1122. https://doi.org/10.1109/TED.2005.848080 (Original work published 2005)
Pavanello, M. A., Martino, J. A., Raskin, J.-P., & Flandre, D. (2005). Analysis on the improved analog performance on double gate transistors by using the graded-channel architecture in a wide temperature range. Solid-State Electronics, Elsevier Science, Pergamon, 49(10), 1569-1575 (October). (Original work published 2005)
Ivanov, P., Laconte, J., Raskin, J.-P., Stankova, M., Sotter, E., Llobet, E., Vilanova, X., Flandre, D., & Correig, X. (2005). SOI-CMOS compatible low-power gas sensor using sputtered and drop-coated metal-oxide active layers. Microsystem Technologies : micro and nanosystems - information storage and processing systems, 12(1-2), 160-168. https://doi.org/10.1007/s00542-005-0003-0 (Original work published 2005)
Kilchytska, V., Levacq, D., Vancaillie, L., & Flandre, D. (2005). On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOICMOS process. Solid-State Electronics, 49(5), 708-715. https://doi.org/10.1016/j.sse.2004.09.004 (Original work published 2005)
Cerdeira, A., Flandre, D., Aleman, M., Pavanello, M. A., Martino, J., & Vancaillie, L. (2005). Advantages of the graded-channel SOIFD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52(5), 967-972. https://doi.org/10.1109/TED.2005.846327 (Original work published 2005)
Papier de conférence
Rue, B., Levacq, D., & Flandre, D. (2005). Low-Power Silicon-on-insulator CMOS Circuits for portable biomedical applications. Proceedings of the Fifth Belgian Day On Biomedical Engineering, 55.
Kilchytska, V., Lederer, D., Simon, P., Collaert, N., Raskin, J.-P., & Flandre, D. (2005). Revised split C-V technique for mobility investigation in advanced devices. 2005 IEEE International SOI Conference (QSIC 2005) (IEEE Cat. No.05CH37694), 110-111.
Hassoune, I., Legat, J.-D., & Flandre, D. (2005). Hybrid full-adder cell in 0.13 µm PD SOI CMOS for low-voltage low-power applications. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits, p. 123-124.
Flandre, D., Cabruja, L., Demeûs, L., Dessard, V., Jorda, X., Manzone, A., Richter, S., Russell, G., & Legat, J.-D. (2005). The ATHIS project: Advanced Techniques for High-Temperature System-on-Chip. International Conference on High Temperature Electronics, HITEN, Paris, France, Paris (France).
Moreno-Hagelsieb, L., Pampin, R., Laurent, G., Raskin, J.-P., Flandre, D., Foultier, B., & Remacle, J. (2005). DNA Electrical Detection Based On Si-CMOS Compatible Al Capacitors and Inductors Coated With Metal Oxides (Concentrations lower than 1 nM). Second Focused Workshop on Electronic Recognition of Bio-molecules, Beckman Institute for Advanced Science and Technology, University of Illinois in Urbana, Illinois (USA).
Pavanello, M. A., Cerdeira, A., Aleman, M. A., Martino, J. A., Vancaillie, L., & Flandre, D. (2005). Low Temperature and Channel Engineering Influence on Harmonic Distortion of SOI NMOSFETs for Analog Applications. Proceedings of the ECS Meeting, SOI Symposium, 125-130.
Bawedin, M., Yun, J. G., Cristoloveanu, S., Lee, H. D., Raynau, C., & Flandre, D. (2005). Meta-Stable DIP (MSD) Effect in Fully-Depleted SOI CMOSFETs. Proceedings of the ECS Meeting, SOI Symposium, 51-56.
Levacq, D., Dessard, V., & Flandre, D. (2005). Ultra-low power flip-flops for MTCMOS circuits. Proceedings of the IEEE International Symposium on Circuits and System (ISCAS 2005), 4681-4684. https://doi.org/10.1109/ISCAS.2005.1465677
Nazarov, A., Houk, Y., Vovk, Ya. N., Lysenko, V. S., & Flandre, D. (2005). High-Temperature Behavior of fully-Depleted SOI MOSFETS in Case of Charge Instability of Buried Oxide. Proceedings of the ECS Meeting, SOI Symposium, 113-118.
Delatte, P., Picun, G., Demeus, L., Simon, P., & Flandre, D. (2005). A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates. In Fesquet, L.; Kaiser, A.; Cristoloveanu, S.; Brillouet, M.; (ed.), Proceedings of ESSCIRC 2005. 31st European Solid-State CircuitsConference (IEEE Cat. No. 05EX1088) (pp. 395-398). IEEE. https://doi.org/10.1109/ESSCIR.2005.1541643
Pavanello, M. A., Cerdeira, A., Martino, J. A., Aleman, M. A., & Flandre, D. (2005). Implementation Of Tunable Resistors Using Graded-Channel SOI MOSFETs Operating In Cryogenic Environments. Proceedings of the 20th International Symposium on Microelectronics Technology and Devices (SBMICRO 2005), 520-528.
Olbrechts, B., Castadot, C., Laconte, J., Flandre, D., & Raskin, J.-P. (2005). SOI-CMOS technology for Thin Film Sensors on Membranes. Proceedings of the 5th Round Table on Micro/Nano Technologies for Space (ESTEC 2005), 213-219.
Moreno, L., Flandre, D., & Gala, J. L. (2005). DNA Hybridization Electrical Detection for Concentrations Lower Than 1nM Target ssDNA, Based on Interdigitated Al/Al2O3 Capacitors. Proceedings of the 2nd Meeting COST ACTION B28 “Array Technologies for BSL3 and BSL4 pathogens”, 520-528.
Flandre, D., Moreno Hagelsieb, L., Pampin, R., Laurent, G., Raskin, J.-P., Foultier, B., & Remacle, J. (2005). DNA analytical CMOS-compatible capacitive systems. Proceedings of the Fifth Belgian Day On Biomedical Engineering, 19-23.
Lederer, D., Kilchytska, V., Rudenko, T., Collaert, N., Flandre, D., Dixit, A., De Meyer, K., & Raskin, J.-P. (2005). FinFET analog characterization from DC to 110 GHz. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2005), p. 99-100. https://doi.org/10.1016/j.sse.2005.07.011
Hassoune, I., Legat, J.-D., & Flandre, D. (2005). Hybrid full-adder cell in 0.13 µm PD SOI CMOS for low-voltage low-power applications. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits, p. 123-124.
Levacq, D., Dessard, V., & Flandre, D. (2005). Ultra-low power flip-flops for MTCMOS circuits. proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat.No. 05CH37618), Vol. 5, p. 4681-4.
Tomaszewski, D., Flandre, D., Renaux, C., Grabiec, P., Kociubinski, A., & Kucharski, K. (2005). Characterization of FD-SOI MOSFETs based on EKV model. Proceedings of the MOS-AK Workshop 2005. MOS-AK Workshop 2005, Grenoble (France).
Raskin, J.-P., Dixit, A., Collaert, N., Rudenko, T., Chung, T. M., Flandre, D., Kilchytska, V., & Lederer, D. (2005). FinFET: a mature multi-gate MOS technology ? A wideband transistor simulation and characterization approach. Proceedings of the SINANO Workshop 2005, Paper n° 5, 21 pages.
Houk, Y., Iniguez, B., Flandre, D., & Nazarov, A. (2005). C infinite - continuous AM SOI pMOSFET Model for High-Temperature Applications. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2005), 95-96.
Moreno Hagelsieb, L., Pampin, R., Laurent, G., Raskin, J.-P., Poleunis, C., Bertrand, P., Flandre, D., Foultier, B., & Remacle, J. (2005). Investigation of the Electrical Detection of hybridized DNA Concentrations lower Than 1 nM, based On CMOS Compatible Al Capacitors Coated With Metal Oxides. Proceedings of the 2nd ERBM Workshop. Published. 2nd ERBM Workshop, Urbana-Champaign University (USA).
Rudenko, T., Kilchytska, V., Collaert, N., De Gendt, S., Rooyackers, R., Jurczak, M., & Flandre, D. (2005). Specific features of the capacitance and mobility behaviors in finfet structures. Proceedings of the 35th European Solid-State Device Research Conference (ESSDERC 2005), 85-88. https://doi.org/10.1109/ESSDER.2005.1546591
Moreno Hagelsieb, L., & Flandre, D. (2005). Anodized Aluminium (Al2O3) Metal-Insulator-Metal (MIM) Capacitors For High Temperature Applications. Proceedings of the 2005 International Conference on High Temperature Electronics (HITEN 2005). 2005 International Conference on High Temperature Electronics (HITEN 2005), Paris (France).
Bawedin, M., Cristoloveanu, S., Yun, J. G., & Flandre, D. (2005). New Memory Effect for Fully Depleted SOI MOSFETs. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2005), 45-46. https://doi.org/10.1016/j.sse.2005.07.019
Gimenez, S. P., Pavanello, M. A., Martino, J. A., & Flandre, D. (2005). Implementation of High Performance Operational Transconductance Amplifiers Using Graded-Channel SOI NMOSFETs. Proceedings of the ECS Meeting, SOI Symposium, 69-74.
Vancaillie, L., Levacq, D., Kilchytska, V., & Flandre, D. (2005). Deep-submicron SOI CMOS mixed-signal circuits for high temperature applications. Proceedings of the 2005 International Conference on High Temperature Electronics (HITEN 2005). 2005 International Conference on High Temperature Electronics (HITEN 2005), Paris (France).
Delatte, P., Simon, P., Demeûs, L., & Flandre, D. (2005). Optimization of Spiral Inductors on High-resistivity SOI Substrates for Low-power LC-VCO Design. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2005), 133-134.
Kilchytska, V., Lederer, D., Simon, P., Collaert, N., Raskin, J.-P., & Flandre, D. (2005). Revised Split C-V Technique for Mobility Investigation in Advanced Devices. In IEEE (ed.), Proceedings of the 2005 IEEE International SOI Conference (pp. 110-111). IEEE. https://doi.org/10.1109/SOI.2005.1563555
Rudenko, T., Collaert, N., De Gendt, S., Kilchytska, V., Jurczak, M., & Flandre, D. (2005). Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode. Proceedings of the INFOS CONFERENCE 2005. INFOS CONFERENCE 2005, Leuven (Belgium).
Flandre, D., Laconte, J., Levacq, D., Afzalian, A., Rue, B., Renaux, C., Iker, F., Olbrechts, B., André, N., & Raskin, J.-P. (2005). SOI CMOS and MEMS for single-chip high-temperature microsystems. Proceedings of the 2005 International Conference on High Temperature Electronics (HITEN 2005), p. Paper n°1.
Bawedin, M., Cristoloveanu, S., & Flandre, D. (2005). Unusual gate current transient behavior in SOI MOSFETs. Proceedings of the 2005 IEEE International SOI Conference (QSIC 2005) (IEEE Cat. No.05CH37694), 67-69.
Gimenez, S. P., Pavanello, M. A., Martino, J. A., & Flandre, D. (2005). Potential Of Improved Gain In Operational Transconductance Amplifier Using 0.5 µm Graded-Channel SOI NMOSFETs For Applications In The Gigahertz Range. Proceedings of SBMICRO 2005, the 20th International Symposium on Microelectronics Technology and Devices, 502-511.
Houk, Y., Nazarov, A., Turchanikov, V. I., Lysenko, V. S., Adriaensen, S., & Flandre, D. (2005). Extraction of charge trapping parameters in FD SOI MOSFET oxides subjected to gamma-irradiation. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2005), 87-88.
Kilchytska, V., Rudenko, T., Collaert, N., Rooyackers, R., Jurczak, M., Raskin, J.-P., & Flandre, D. (2005). Mobility characterization in FinFETs using split C-V technique. Proceedings of the 6th International Conference on Ultimate integration of Silicon (ULIS 2005), 117-120.
Bawedin, M., Cristoloveanu, S., & Flandre, D. (2005). Unusual gate current transient behavior in SOI MOSFETs. In IEEE (ed.), Proceedings of the 2005 IEEE International SOI Conference (pp. 67-69). https://doi.org/10.1109/SOI.2005.1563536
Rue, B., & Flandre, D. (2005). Architecture de préamplificateur CMOS SOI faible bruit basse consommation pour signaux physiologiques. Proceedings of TAISA 2005 - 6ème Colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications. 6ème Colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications (TAISA 2005), Marseille (France).
Monographie
Flandre, D., & Nazarov, A. (2005). Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment. Kluwer Academic Publishers.
Brevet
Levacq, D., Dessard, V., Adriaensen, S., & Flandre, D. (2005). ULP basic blocks and their uses (Patent No. 10/602,016).
Chapitre de livre
Rudenko, T., & Kilchytska, V. (2005). Characterization of Carrier Generation in Thin-Film SOI Devices By Reverse Gated-Diode Technique and Its Application At High Temperatures. In D. Flandre, A.N. Nazarov, P.L.F. Hemment (ed.), Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment Proceedings of the NATO Advanced Research Workshop on Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment Kiev, Ukraine 26–30 April 2004 (pp. 247-254). Kluwer Academic Publ. https://doi.org/10.1007/1-4020-3013-4_27
Article de journal
Lederer, D., Flandre, D., & Raskin, J.-P. (2004). AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs. IEEE Electron Device Letters, 25(2), 104-106. https://doi.org/10.1109/LED.2003.822658 (Original work published 2004)
Rudenko, T., Flandre, D., Rudenko, A., Kilchytska, V., Cristoloveanu, S., Ernst, T., Colinge, J.-P., & Dessard, V. (2004). Determination of film and surface recombination in thin-film SOI devices using gated-diode technique. Solid-State Electronics, 48(3), 389-399. https://doi.org/10.1016/j.sse.2003.09.004 (Original work published 2004)
Laconte, J., Dupont, C., Flandre, D., & Raskin, J.-P. (2004). SOI CMOS compatible low-power microheater optimization for the fabrication of smart gas sensors. IEEE Sensors Journal, 4(5), 670-680. https://doi.org/10.1109/JSEN.2004.833516 (Original work published 2004)
Kranti, A., Flandre, D., Chung, T. M., & Raskin, J.-P. (2004). Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications. Solid-State Electronics, 48(6), 947-959. https://doi.org/10.1016/j.sse.2003.12.014 (Original work published 2004)
Neve, A., Schettler, H., Ludwig, T., & Flandre, D. (2004). Power-delay product minimization in high-performance 64-bit carry-select adders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(3), 235-244. https://doi.org/10.1109/TVLSI.2004.824305 (Original work published 2004)
Moreno Hagelsieb, L., Flandre, D., Lobert, P., Pampin, R., Bourgeois, D., & Remacle, J.-F. (2004). Sensitive DNA electrical detection based on interdigitated Al/Al2O3 microelectrodes. Sensors and Actuators B: Chemical : international journal devoted to research and development of physical and chemical transducers, 98(2-3), 269-274. https://doi.org/10.1016/j.snb.2003.10.036 (Original work published 2004)
Haddab, Y., Mosser, V., Lysowec, M., Suski, J., Demeûs, L., Renaux, C., Adriaensen, S., & Flandre, D. (2004). Low-Noise SOI Hall Devices. Fluctuation and Noise Letters : an interdisciplinary scientific journal on random processes in physical, biological and technological systems, 4(2), L345-L354. https://doi.org/10.1142/S021947750400194X (Original work published 2004)
Bawedin, M., Flandre, D., & Renaux, C. (2004). LDMOS in SOI technology with very-thin silicon film. Solid-State Electronics, 48(12), 2263-2270. https://doi.org/10.1016/j.sse.2004.06.007 (Original work published 2004)
Laconte, J., Iker, F., Jorez, S., André, N., Proost, J., Pardoen, T., Flandre, D., & Raskin, J.-P. (2004). Thin films stress extraction using micromachined structures and wafer curvature measurements. Microelectronic Engineering, 76(1-4), 219-226. https://doi.org/10.1016/j.mee.2004.07.003 (Original work published 2004)
Cerdeira, A., Flandre, D., Aleman, M., & Estrada, M. (2004). Integral function method for determination of nonlinear harmonic distortion. Solid-State Electronics, 48(12), 2225-2234. https://doi.org/10.1016/j.sse.2004.06.001 (Original work published 2004)
Levacq, D., Flandre, D., Liber, C., & Dessard, V. (2004). Composite ULP diode fabrication, modelling and applications in multi-V-th FD SOICMOS technology. Solid-State Electronics, 48(6), 1017-1025. https://doi.org/10.1016/j.sse.2003.12.016 (Original work published 2004)
Papier de conférence
Kilchytska, V., Collaert, N., Rooyackers, R., Lederer, D., Raskin, J.-P., & Flandre, D. (2004). Perspective of FinFETs for analog applications. Proceedings of the 34rd European Solid-State Device Research Conference (ESSDERC 2004), 65-68. https://doi.org/10.1109/ESSDER.2004.1356489
Moreno Hagelsieb, L., Foultier, B., Laurent, G., Poleunis, C., Bertrand, P., Raskin, J.-P., Remacle, J., & Flandre, D. (2004). Aluminium anodizing process characterization for DNA attachment and electrical detection. In Thomas Laurell (ed.), Proceedings of [Mu]TAS 2004 8th International Conference on Miniaturized Systems for Chemistry and Life Sciences, Malmö, Sweden, September 26-30, 2004 (pp. 395-397). RSC.
Picos, R., Roca, M., Iniguez, B., Bellodi, M., Flandre, D., & Garcia-Moreno, E. (2004). Direct MOSFET Parameters Extraction Using Fourier-Space Techniques. Proceedings of the Fifth International Caracas Conference on Devices, Circuits and Systems, 9-13. https://doi.org/10.1109/ICCDCS.2004.1393344
Vancaillie, L., Hervé, Y., & Flandre, D. (2004). Méthodologie de dimensionnement basse puissance et modélisation VHDL-AMS d’un modulateur sigma delta en temps continu. In EPFL (ed.), Proceedings of TAISA 2004 - 5ème Colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications (pp. 69-72).
Balestra, F., Parker, E., Flandre, D., Kurz, H., Sangiorgi, E., & Ghibaudo, G. (2004). SINANO: SILICON-BASED NANODEVICES EUROPEAN NETWORK OF EXCELLENCE OF THE 6th FRAMEWORK PROGRAMME. Proceedings of the Ultimate Lithography and Nanodevice Engineering (LITHO 2004). Ultimate Lithography and Nanodevice Engineering (LITHO 2004), Agelonde (France).
Rudenko, T., Kilchytska, V., & Flandre, D. (2004). Characterization of Carrier Generation in Thin-Film SOI Devices by Reverse Gated-Diode Technique and Its Application at High Temperatures. In D. Flandre, A. Nazarov, P.L.F. Hemment (ed.), Proceedings of the NATO Advanced Research Workshop - Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment (pp. 76-77).
Pavanello, M. A., Cerdeira, A., Martino, J. A., Aleman, M. A., & Flandre, D. (2004). Analysis of harmonic distorsion in graded-channel SOI MOSFETS at high temperatures. In Santos E.J.P., Ribas R.P., Swart J. Eds. (ed.), Proceedings of the Nineteenth International Symposium on Microelectronics Technology and Devices (SBMICRO 2004) (pp. 39-44).
Denef, N., Moreno Hagelsieb, L., Laurent, G., Pampin, R., Foultier, B., Remacle, B., Flandre, D., & Raskin, J.-P. (2004). RF detection of DNA based on CMOS inductive and capacitive sensors. Conference Proceedings. 34th European Microwave Conference (IEEE Cat.No.04EX963), Vol. 2, p. 669-72.
Parvais, B., Delatte, P., Matsuhashi, H., Ichikawa, F., Simon, P., Schreurs, D., Flandre, D., & Raskin, J.-P. (2004). Small- and Large-Signal RF Characterization of Fully-Depleted Accumulation-mode Varactors for Low-Voltage LC-VCO SOI Design. In IEEE (ed.), Proceedings of the 2004 IEEE International SOI Conference (pp. 168-170). IEEE. https://doi.org/10.1109/SOI.2004.1391602
Kilchytska, V., Vancaillie, L., de Meyer, K., & Flandre, D. (2004). Temperature dependence of RF losses in HR SOI substrates. Proceedings of the NATO Advanced Research Workshop - Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment, 52-53.
Ivanov, P. T., Laconte, J., Raskin, J.-P., Stankova, M., Sotter, E., Llobet, E., Vilanova, X., Flandre, D., & Correig, X. (2004). SOI-CMOS compatible low-power gas sensor using sputtered and drop-coated metal-oxide active layers. Proceedings of the Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2004), 160-168.
Donckers, N., Butaye, O., Flandre, D., & Verleysen, M. (2004). Point mémoire analogique basse tension basé sur l’effet GIDL. Proceedings of TAISA 2004 - 5ème Colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications, 55-58.
Kilchytska, V., de Meyer, K., & Flandre, D. (2004). In-depth investigation of 0.13µm SOI MOSFETs for high-temperature applications. Proceedings of the 5th European Workshop on Ultimate Integration of Silicon (ULIS 2004), 163-166.
Hassoune, I., Nève, A., Legat, J.-D., & Flandre, D. (2004). Branch-Based Design of Carry Calculation Cell for Ultra-Low Power and High-Temperature Applications. Proceedings of HITECH 2004, p. 6.
Moreno Hagelsieb, L., Lobert, P. E., Pampin, R., Remacle, J., & Flandre, D. (2004). DNA Detection Based on Capacitive Al/Al2O3 Microelectrodes. Proceedings of the 17th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2004), 308-311. https://doi.org/10.1109/MEMS.2004.1290584
Houk, Y., Nazarov, A. N., Turchanikov, V. I., Lysenko, V. S., Adriaensen, S., & Flandre, D. (2004). Radiation effect on electrical properties of fully-depleted UNIBOND SOI MOSFETS. Proceedings of the NATO Advanced Research Workshop - Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment, 67-68.
Laconte, J., Iker, F., André, N., Pardoen, T., Proost, J., Flandre, D., & Raskin, J.-P. (2004). Thin films stress extraction using micromachined structures and wafer curvature measurements. Proceedings of the Workshop on advanced microelectronics materials, Materials for Advanced Metallization (MAM 2004), paper 03.2.
Denef, N., Moreno Hagelsieb, L., Laurent, G., Foultier, B., Remacle, J., Flandre, D., & Raskin, J.-P. (2004). RF detection of DNA based on CMOS inductive and capacitive sensors. Proceedings of the 34th European Microwave Week 2004 (EuMC 2004), 669-672.
Levacq, D., Dessard, V., & Flandre, D. (2004). Recent advances in SOI MOSFETs devices and circuits for ultra-low power / high temperature applications. Proceedings of the NATO Advanced Research Workshop - Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment, 41-42.
Flandre, D., Pampin, R., Hagelsieb, L. M., Laurent, G., Raskin, J.-P., Foultier, B., & Remacle, J. (2004). On-chip DNA electrical detection based on Si-CMOS compatible Al capacitors and inductors coated with metal oxides. Proceedings of the The First Focused Workshop on Electronic Recognition of DNA Molecules, 36 pages.
Takatori, K., & Flandre, D. (2004). Revised EKV Model to Apply gm/Id Methodology to Poly-Si TFT Analog Design. Proceedings of the 11th International Conference Mixed Design of Integrated Circuits and Systems. 11th International Conference Mixed Design of Integrated Circuits and Systems, Szczecin (Poland).
Hassoune, I., Legat, J.-D., Neve, A., & Flandre, D. (2004). Investigation of low-power low-voltage circuit techniques for a hybrid full-adder cell. Lecture Notes in Computer Science, 3254, 189-197. (Original work published 2004)
Afzalian, A., & Flandre, D. (2004). Physical Modelling and Design of thin film SOI lateral PIN Photodiodes for Blue DVD-applications. Proceedings of the 2004 IEEE International SOI Conference, p. 21-23. https://doi.org/10.1109/SOI.2004.1391538
Cerdeira, A., Aleman, M. A., Pavanello, M. A., Martino, J. A., Vancaillie, L., & Flandre, D. (2004). On-Resitance and Harmonic Distorsion in Graded-Channel SOI FD MOSFET. Proceedings of the Fifth International Caracas Conference on Devices, Circuits and Systems, 118-121. https://doi.org/10.1109/ICCDCS.2004.1393365
Bawedin, M., Cristoloveanu, S., & Flandre, D. (2004). Unusual Floating Body Effect in Fully Depleted MOSFETs. In IEEE (ed.), Proceedings of the 2004 IEEE International SOI Conference (pp. 151-152). IEEE. https://doi.org/10.1109/SOI.2004.1391595
de Souza, M., Pavanello, M. A., Iniguez, B., & Flandre, D. (2004). A Fully Analytical Continuous Model for Graded-Channel SOI MOSFET for Analog Applications. In Santos E.J.P., Ribas R.P., Swart J. Eds. (ed.), Proceedings of the 19th International Symposium on Microelectronics Technology and Devices (SBMICRO 2004) (pp. 27-32). The Electrochemical Society (ECS).
Conde, J. E., Cerdeira, A., & Flandre, D. (2004). Comparison between Nonlinear Characteristics of N-channel and P-channel FD SOI MOSFETs. Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 122-125. https://doi.org/10.1109/ICCDCS.2004.1393366
Flandre, D., Laconte, J., Levacq, D., Afzalian, A., Rue, B., Renaux, C., Iker, F., Olbrechts, B., André, N., & Raskin, J.-P. (2004). SOI technology for single-chip harsh environment microsystems. Proceedings of the Conference on Micro-Nano-Technologies for Aerospace Applications (CANEUS 2004), 157-169.
Kilchytska, V., Vancaillie, L., de Meyer, K., & Flandre, D. (2004). MOSFETs scaling down: advantages and disadvantages for high temperature applications. In Denis Flandre, Alexei N. Nazarov, Peter L.F. Hemment (ed.), Proceedings of the NATO Advanced Research Workshop on Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment (pp. 185-190). https://doi.org/10.1007/1-4020-3013-4_19
Hassoune, I., Levacq, D., Drummond, A., Gaudissart, A., Legat, J.-D., & Flandre, D. (2004). A Hybrid Full-adder Cell for High-Performance and Low-Power Design. Proceedings of the 11th Electronic Devices and Systems Conference 2004 (EDS′04), p. 154-159.
Laconte, J., Rue, B., Raskin, J.-P., & Flandre, D. (2004). Fully CMOS-SOI Compatible Low-Power Directional Flow Sensor. In IEEE, TU Vienna (ed.), Proceedings of the Third IEEE International Conference on Sensors 2004 (pp. 864-867). IEEE. https://doi.org/10.1109/ICSENS.2004.1426307
Laconte, J., Rue, B., Raskin, J.-P., & Flandre, D. (2004). Fully CMOS-SOI compatible low-power directional flow sensor. In Rocha, D.; Sarro, P.M.; Vellekoop, M.J.; (ed.), Proceedings of the IEEE Sensors 2004 (IEEE Cat. No.04CH37603) (p. Vol. 2, p. 864-7). IEEE.
Kilchytska, V., Levacq, D., Vancaillie, L., & Flandre, D. (2004). On the great potential of non-doped SOI MOSFETs for analog applications. In IMEC (ed.), Proceedings of the 5th European Workshop on Ultimate Integration of Silicon (ULIS 2004) (pp. 137-140).
Godignon, P., Vellvehi, M., Flores, D., Millan, J., Moreno Hagelsieb, L., & Flandre, D. (2004). Development of high-voltage high-current DMOS transistor compatible with high-temperature thin-film SOI CMOS applications. Proceedings of the NATO Advanced Research Workshop - Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment, 96-97.
Davanzzo Gomes dos Santos, C., Pavanello, M. A., Martino, J. A., Flandre, D., & Raskin, J.-P. (2004). Behaviour of Graded Channel SOI Gate-All-Around NMOSFET Devices at High Temperatures. In Santos E.J.P., Ribas R.P., Swart J. Eds. (ed.), Proceedings of the Nineteenth International Symposium on Microelectronics Technology and Devices (SBMICRO 2004) (pp. 9-14). The Electrochemical Society (ECS).
Bawedin, M., & Flandre, D. (2004). Optimization and Characterization of LDMOS Transistor in Thin Film SOI. Proceedings of the NATO Advanced Research Workshop - Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment, 82-83.
Monographie
Silveira, F., & Flandre, D. (2004). Low Power Analog CMOS For Cardiac Pacemakers: Design and Optimization in Bulk and SOI Technologies. Springer-Verlag New York Inc.
Chapitre de livre
Flandre, D. (2004). SOI Technology: A viable alternative to bulk CMOS. In Valle, Maurizio (ed.) (ed.), Smart Adaptive Systems on Silicon (p. p. 49-64). Kluwer Academic.
Godignon, P., Vellvehi, M., Flores, D., Millan, J., & Moreno Hagelsieb, L. (2004). High-Voltage High-Current DMOS Transistor Compatible with High-Temperature Thin-Film SOI CMOS Applications. In D. Flandre, A.N. Nazarov, P.L.F. Hemment (ed.), Proceedings of the NATO Advanced Research Workshop on Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment (p. p. 279-284). Kluwer Academic Publishers.
Levacq, D., Dessard, V., & Flandre, D. (2004). Recent advances in SOI MOSFET devices and circuits for ultra-low power / high temperature applications. In D. Flandre, A.N. Nazarov, P.L.F. Hemment (ed.), Proceedings of the NATO Advanced Research Workshop on Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment (p. p. 133-144). Kluwer Academic Publishers. https://doi.org/10.1007/1-4020-3013-4_14
Houk, Y., Nazarov, A. N., Turchanikov, V. I., Lysenko, V. S., Adriaensen, S., & Flandre, D. (2004). Radiation Effect On Electrical Properties Of Fully-Depleted Unibond SOI MOSFETS. In D. Flandre, A.N. Nazarov, P.L.F. Hemment (ed.), Proceedings of the NATO Advanced Research Workshop on Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment (p. p. 233-239). Kluwer Academic Publishers.
Article de journal
Kilchytska, V., Flandre, D., Neve, A., Vancaillie, L., Levacq, D., Adriaensen, S., van Meer, H., De Meyer, K., Raynaud, C., Dehan, M., & Raskin, J.-P. (2003). Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Transactions on Electron Devices, 50(3), 577-588. https://doi.org/10.1106/TED.2003-810471 (Original work published 2003)
Flandre, D., & Raskin, J.-P. (2003). Circuits et capteurs intelligents intégrés en technologie CMOS SOI pour environnements et applications hétérogènes. Nano et Micro Technologies, 3(1-2), 183-200. (Original work published 2003)
Afzalian, A., & Flandre, D. (2003). Modeling of the bulk versus SOICMOS performances for the optimal design of APS circuits in low-power low-voltage applications. IEEE Transactions on Electron Devices, 50(1), 106-110. https://doi.org/10.1109/TED.2002.806957 (Original work published 2003)
Iniguez, B., Flandre, D., Raskin, J.-P., Simon, P., & Segura, J. (2003). A review of leakage current in SOI CMOS ICs: impact on parametric testing techniques. Solid-State Electronics, 47(11), 1959-1967. https://doi.org/10.1016/S0038-1101(03)00249-1 (Original work published 2003)
Kilchytska, V., Flandre, D., Levacq, D., Lederer, D., & Raskin, J.-P. (2003). Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs. IEEE Electron Device Letters, 24(6), 414-416. https://doi.org/10.1109/LED.2003.813373 (Original work published 2003)
Estrada, M., Flandre, D., Afzalian, A., Cerdeira, A., Baez, H., & de Lucca, A. (2003). FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si : H photodiode. Microelectronics Reliability, 43(2), 189-193. https://doi.org/10.1016/S0026-2714(02)00288-3 (Original work published 2003)
Lobert, P., Flandre, D., Bourgeois, D., Pampin, R., Akheyar, A., Hagelsieb, L., & Remacle, J.-F. (2003). Immobilization of DNA on CMOS compatible materials. Sensors and Actuators B: Chemical : international journal devoted to research and development of physical and chemical transducers, 92(1-2), 90-97. https://doi.org/10.1016/S0925-4005(03)00096-0 (Original work published 2003)
Papier de conférence
Lederer, D., Dehan, M., Vanhoenacker-Janvier, D., Flandre, D., & Raskin, J.-P. (2003). Frequency degradation of SOI MOS device output conductance. Proceedings of the 2003 IEEE International SOI Conference, 76-77. https://doi.org/10.1109/SOI.2003.1242905
Levacq, D., Adriaensen, S., Liber, C., Dessard, V., & Flandre, D. (2003). Conception de circuits analogiques micro-puissance en technologie CMOS-SOI. Proceedings of TAISA 2003, 95-98.
Kilchytska, V., Chung, T. M., van Meer, H., De Meyer, K., Raskin, J.-P., & Flandre, D. (2003). Investigation of charge control related performances in double-gate SOI MOSFETs. Proceedings of the 11th International Symposium Silicon-on-Insulator Technology and Devices, 225-230.
Levacq, D., Dehan, M., Flandre, D., & Raskin, J.-P. (2003). Figures-of-Merit Of Intrinsic, Standard-Doped And Graded-Channel SOI And SOS MOSFETs For Analog Baseband And RF Applications. Proceedings of the ECS 11th International Symposium on SOI Technology and Devices, 295-300.
Lederer, D., Dehan, M., Vanhoenacker-Janvier, D., Flandre, D., & Raskin, J.-P. (2003). Frequency degradation of SOI MOS device output conductance. 2003 IEEE International SOI Conference. Proceedings (Cat. No.03CH37443), 76-77.
Laurent, G., Moreno Hagelsieb, L., Lederer, D., Lobert, P. E., Flandre, D., Remacle, J.-F., & Raskin, J.-P. (2003). DNA electrical detection based on inductor resonance frequency in standard CMOS technology. In Franca, J.; Freitas, P. (ed.), Proceedings of the 29th European Solid-State Device Research (ESSDERC ’03) (pp. 171-174). IEEE. https://doi.org/10.1109/ESSCIRC.2003.1257141
Adriaensen, S., & Flandre, D. (2003). High-Temperature Accurate Characterization of SOI Bipolar/Diode Devices for their Applications in Precise High-Order Bandgap References. In Johnston C., Vermessan O., Crossley A. (ed.), Proceedings of the 2003 International Conference on High-Temperature Electronics (HITEN 2003) (pp. 133-140).
Laconte, J., Wilmart, V., Raskin, J.-P., & Flandre, D. (2003). High-sensitivity capacitive humidity sensor using 3-layer patterned polyimide sensing film. Proceedings of IEEE Sensors 2003, 372-377. https://doi.org/10.1109/ICSENS.2003.1278961
Vancaillie, L., Silveira, F., Linares-Barranco, B., Serrano-Gotarredona, T., & Flandre, D. (2003). MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design. In Franca, J.; Koch, R.; (ed.), ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat.No.03EX705) (pp. 671-674). IEEE.
Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J.-P., & Flandre, D. (2003). Operation of double gate graded-channel transistors at low temperatures. Proceedings of the Seventh International Symposium on Low Temperature Electronics, 50-60.
Bawedin, M., Estrada, M., & Flandre, D. (2003). Investigation of Floating Body Effects on SOI MOSFET Gate Tunneling Currents. Proceedings of the 4th European Workshop on ULtimate Integration of Silicon (ULIS 2003), 45-48.
Levacq, D., Vancaillie, L., & Flandre, D. (2003). Potential of SOI intrinsic MOSFETs for ring VCO design. Proceedings of the 2003 IEEE International SOI Conference, 17-18. https://doi.org/10.1109/SOI.2003.1242880
Sanz, M. T., Celma, S., Calvo, B., & Flandre, D. (2003). Comparison of Graded-Channel and Self-Cascode SOI MOS Transistors. Proceedings of the 4ª Conferencia de Dispositivos Electrónicos (CDE-2003), II-11.
Afzalian, A., & Flandre, D. (2003). Measurements, Modelling and Electrical Simulations of Lateral PIN Photodiodes in Thin Film-SOI for High Quantum Efficiency and High Selectivity in the UV range. Proceedings of the 33rd European Solid-State Device Research Conference (ESSDERC 2003), p. 55-58. https://doi.org/10.1109/ESSDERC.2003.1256809
Flandre, D. (2003). Nanotechnologies pour circuits intégrés et capteurs intelligents. Proceedings du Colloque “Les Nanotechnologies, pari gagnant pour l’Industrie”,. Colloque “Les Nanotechnologies, pari gagnant pour l’Industrie”, Charleroi (Belgium).
Nazarov, A. N., Lysenko, V. S., Colinge, J.-P., & Flandre, D. (2003). Nature of High-Temperature Charge Instability of Fully Depleted SOI MOSFETs. In S.Cristoloveanu (ed.), Proceedings of the 11th International Symposium «Silicon-on-Insulator Technology and Devices” (pp. 455-460).
Delatte, P., Picun, G., Demeûs, L., Vancaillie, L., Kilchytska, V., Flandre, D., Kawai, Y., & Ichikawa, F. (2003). On the Potential 0.2 µm Fully-Depleted SOI for Low-power Mixed and Digital Circuits for Applications up to 225°C. In Johnston C., Vermessan O., Crossley A. (ed.), Proceedings of the 2003 International Conference on High Temperature Electronics (HITEN 2003) (pp. 105-110).
Takatori, K., & Flandre, D. (2003). Comparison of SOI, poly-Si TFT and bulk Si MOS performance using gm/ID methodology. In S.Cristoloveanu (ed.), Proceedings of the 11th International Symposium «Silicon-on-Insulator Technology and Devices” (pp. 301-306).
Sanz, M. T., Celma, S., Calvo, B., & Flandre, D. (2003). Self-Cascode SOI versus Graded-Channel SOI MOS Transistors for Low-Voltage Applications. Proceedings of the European Conference on Circuit Theory and Design (ECCTD′03), I-157 to I-160.
Vancaillie, L., Kilchytska, V., Delatte, P., Matsuhashi, H., Ichikawa, F., & Flandre, D. (2003). 0.15µm Fully Depleted SOI for Mixed-Signal Applications up to 250°C: Are We Approaching the Limits of Device Scaling for High-Temperature Electronics ? In Johnston C., Vermessan O., Crossley A. (ed.), Proceedings of the 2003 International Conference on High Temperature Electronics (HITEN 2003) (pp. 127-132).
Vancaillie, L., Kilchytska, V., Delatte, P., Demeûs, L., Matsuhashi, H., Ichikawa, F., & Flandre, D. (2003). Peculiarities of the temperature behaviour of SOI MOSFET’s in the deep submicron area. Proceedings of the 2003 IEEE International SOI Conference, 78-79. https://doi.org/10.1109/SOI.2003.1242906
Vancaillie, L., Silveira, F., Linares-Barranco, B., Serrano-Gotarredona, T., & Flandre, D. (2003). MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design. Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC 2003), 671-674. https://doi.org/10.1109/ESSCIRC.2003.1257224
Neve, A., Quisquater, J.-J., & Flandre, D. (2003). SOI technology for future high-performance smart cards. IEEE Micro, 23(3), 58-67. https://doi.org/10.1109/MM.2003.1209467 (Original work published 2003)
Cerdeira, A., Aleman, M. A., Estrada, M., Flandre, D., Parvais, B., Raskin, J.-P., & Picun, G. (2003). The Integral Function Method: A New Method to Determine the Non-linear Harmonic Distortion. Proceedings of the 18th International symposium on microelectronics technology and devices 5sbmicro 2003), 131-146.
Adriaensen, S., Flandre, D., & Richter, S. (2003). Conception d’une tension de référence bandgap d’ordre supérieur fonctionnant de 25 à 225°C dans une technologie CMOS-SOI 1.0 µm partiellement déplétée. Proceedings de TAISA 2003, 87-90.
Levacq, D., Liber, C., Dessard, V., & Flandre, D. (2003). Ultra Low-Power design techniques using special SOI MOS diodes. Proceedings of the 2003 IEEE International SOI Conference, 19-20. https://doi.org/10.1109/SOI.2003.1242881
Kranti, A., Chung, T. M., Flandre, D., & Raskin, J.-P. (2003). Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications. Proceedings of the 33rd European Solid-State Device Research Conference (ESSDERC 2003), 131-134. https://doi.org/10.1109/ESSDERC.2003.1256828
Gimenez, S. P., Pavanello, M. A., Martino, J. A., Adriaensen, S., & Flandre, D. (2003). Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI 2003), 26-31. https://doi.org/10.1109/SBCCI.2003.1232802
Haddab, Y., Mosser, V., Lysowec, M., Suski, J., Demeûs, L., Renaux, C., Adriaensen, S., & Flandre, D. (2003). Low-noise SOI Hall devices. Proceedings of SPIE Fluctuations and Noise Symposium, 196-203. https://doi.org/10.1117/12.490185
Laconte, J., Wilmart, V., Raskin, J.-P., & Flandre, D. (2003). Capacitive Humidity Sensor Using a Polyimide Sensing Film. Proceedings of the Symposium on Design, Test, Integration, and Packaging of MEMS/MOEMS 2003, 223-228. https://doi.org/10.1109/DTIP.2003.1287041
Remacle, J., Alexandre, I., Moreno Hagelsieb, L., Pampin, R., & Flandre, D. (2003). Nano and micro metal particles for molecular detection. Proceedings of the International Symposium on Bioconjugated Nanoparticles in Molecular Diagnostics and Therapy. Published. International Symposium on Bioconjugated Nanoparticles in Molecular Diagnostics and Therapy, Jena (Germany).
Dessard, V., Picun, G., Delatte, P., Demeûs, L., & Flandre, D. (2003). Versatile high performance Voltage Regulator for high temperature applications. Proceedings of the 2003 International Conference on High Temperature Electronics (HITEN 2003), 121-126.
Levacq, D., Dessard, V., & Flandre, D. (2003). A Novel CMOS Memory Cell Architecture for Ultra-Low Power Applications Operating up to 280°C. Proceedings of the ECS 11th International Symposium on SOI Technology and Devices, 249-254.
Silveira, F., Flandre, D., & Aguirre, P. (2003). Conception optimale et réutilisable d’OTAs pour dispositifs médicaux implantables. Proceedings of the TAISA 2003, 105-110.
Pampin, R., Moreno Hagelsieb, L., Lobert, P.-E., Géry, L., Raskin, J.-P., Remacle, J., & Flandre, D. (2003). Integrated Low-Cost Micro-Sensors for DNA Sensitive Electrical Detection. Proceedings of the ASM Conference on Bio-, Micro-, and Nanosystems, 25 - Abstract n°16, 2 posters.
Afzalian, A., & Flandre, D. (2003). Méthodologie de conception d’un photorécepteur intégré et son application en technologie CMOS-SOI. Proceedings of TAISA 2003, p. 131-134.
Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J.-P., & Flandre, D. (2003). Impact of the Graded-Channel Architecture on Double Gate Transistors for High-Performance Analog Applications. In S. Cristoloveanu (ed.), Proceedings of the 11th International Symposium Silicon-on-Insulator Technology and Devices (pp. 261-266).
Papier de conférence
Levacq, D., Vancaillie, L., & Flandre, D. (2002). Etude d’un oscillateur en anneau micropuissance à 433MHz intégré en technologie CMOS/SOS. Proceedings du Colloque TAISA 2002. Colloque TAISA 2002, Paris (France).
Kilchytska, V., Levacq, D., Lederer, D., Raskin, J.-P., & Flandre, D. (2002). Influence of the substrate on the small-signal characteristics of SOI MOSFETs. GSEC Graduate School in Electronics and Communications, Belgium.
Vancaillie, L., Kilchytska, V., Levacq, D., Dessard, V., Demeûs, L., & Flandre, D. (2002). Electrical characterization of an industrial SOS-CMOS process up to 300°C. Proceedings of the 6th High Temperature Electronics Conference (HITEC), 10-17.
Pavanello, M. A., Iniguez, B., Flandre, D., & Martino, J. A. (2002). A physically-based continuous model for graded-channel SOI MOSFET. Proceedings of the XVII SBMicro Microelectronics Technology and Devices (ECS 2002), p. 35-44.
Cerdeira, A., Estrada, M., Flandre, D., Ortiz-Conde, A., & Sanchez, F. J. G. (2002). Generalization of the Integral Function Method to Evaluate Distorsion in SOI FD MOSFET. Proceedings of the 23rd International Conference on Microelectronics (MIEL 2002), 443-446. https://doi.org/10.1109/MIEL.2002.1003294
Flandre, D., Adriaensen, S., Afzalian, A., Laconte, J., Levacq, D., Renaux, C., Vancaillie, L., Raskin, J.-P., Demeûs, L., Delatte, P., Dessard, V., & Picun, G. (2002). Intelligent SOI CMOS Integrated Circuits and Sensors for Heterogeneous Environments and Applications. Proceedings of the IEEE Sensors 2002, p. 1407-1412. https://doi.org/10.1109/ICSENS.2002.1037327
Laconte, J., Dupont, C., Akheyar, A., Raskin, J.-P., & Flandre, D. (2002). Fully CMOS compatible low-power microheater. Proceedings of SPIE - the International Society for Optical Engineering, 634-644.
Flandre, D. (2002). Méthodologie gm/ID: un chaînon entre l’analyse symbolique et la synthèse de circuits analogiques basse puissance. Proceedings du Colloque TAISA 2002. Colloque TAISA 2002, Paris (France).
Neve, A., Flandre, D., Schettler, H., Ludwig, T., & Hellner, G. (2002). Design of a branch-based 64-bit carry-select adder in 0.18 mu m partially depleted SOI CMOS. ISLPED′02: Proceedings of the 2002 International Symposium on LowerPower Electronics and Design (IEEE Cat. No.02TH8643), 108-111. https://doi.org/10.1109/LPE.2002.1029565
Vanmackelberg, M., Raynaud, C., Faynot, O., Pelloie, J., Tabone, C., Grouillet, A., Martin, F., Dambrine, G., Picheta, L., Mackowiak, E., Llinares, P., Sevenhans, J., Compagne, E., Fletcher, G., Flandre, D., Dessard, V., Vanhoenacker-Janvier, D., & Raskin, J.-P. (2002). 0.25 mu m fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters. Solid-State Electronics, 46(3), 379-386. (Original work published 2002)
Berger, G., Moreno Hagelsieb, L., Martinez, I., Akheyar, A., Harboe Sorensen, R., Ryckewaert, G., & Flandre, D. (2002). Edge Effects and Tilt Dependency of Heavy Ion Irradiation SEE Characterization In PN junctions. Proceedings of the RADECS conference 2002. RADECS conference 2002, Padova (Italy).
Kilchytska, V., Levacq, D., Lederer, D., Raskin, J.-P., & Flandre, D. (2002). Substrate effects on the small-signal characteristics of SOI MOSFET’s. Proceedings of the 32nd European Solid-State Device Research Conference (ESSDERC 2002), 519-522. https://doi.org/10.1109/ESSDERC.2002.194982
Pavanello, M. A., Iniguez, B., Martino, J. A., & Flandre, D. (2002). A physically-based continuous analytical graded-channel SOI nMOSFET model for analog applications. Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems, D030-1 - D030-5. https://doi.org/10.1109/ICCDCS.2002.1004044
Laconte, J., Dupont, C., Flandre, D., & Raskin, J.-P. (2002). SOI CMOS compatible low-power microheater optimization and fabrication for smart gas sensor implementations. Proceedings of IEEE Sensors 2002. First IEEE International Conferenceon Sensors (Cat. No.02CH37394), 1395-1400. https://doi.org/10.1109/ICSENS.2002.1037325
Neve, A., & Flandre, D. (2002). Design of a branch-based carry-select adder IP portable in 0.25 mu m bulk and silicon-on-insulator CMOS technologies. In Robert, M.; Rouzeyre, B.; Piquet, C.; Flottes, M.-L.; (ed.), SOC Design Methodologies. IFIP TC10/WG10.5 Eleventh InternationalConference on Very Large Scale Integration of Systems-on-Chip(VLSI-SOC′01) (pp. 169-180). Kluwer academic publishers.
Estrada, M., Afzalian, A., Flandre, D., Cerdeira, A., Baez, H., & de Lucca, A. (2002). FD MOS SOI circuit to improve the threshold of detection of a co-integrated amorphous photodiode. Proceedings of the Iberchip workshop, 5.
Adriaensen, S., Dessard, V., & Flandre, D. (2002). A voltage reference compatible with standard SOI CMOS processes and consuming 1 pA to 50 nA from room temperature up to 300 degrees C. 2002 IEEE International SOI Conference. Proceedings (Cat. No.02CH37347), 130-131. https://doi.org/10.1109/SOI.2002.1044448
Silveira, F., & Flandre, D. (2002). A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS′2002), 181-184.
Vancaillie, L., Kilchytska, V., Levacq, D., Adriaensen, S., van Meer, H., De Meyer, K., Torrese, G., Raskin, J.-P., & Flandre, D. (2002). Influence of HALO implantation on analog performances and comparison between bulk, Partially-Depleted and Fully-Depleted MOSFETs. Proceedings of the 2002 IEEE International SOI Conference, 161-162. https://doi.org/10.1109/SOI.2002.1044459
Pavanello, M. A., Martino, J. A., & Flandre, D. (2002). Analog performance of graded-channel SOI nMOSFETs at low temperatures. Proceedings of the XVII SBMicro Microelectronics Technology and Devices (ECS 2002), 21-27.
Kervyn, T., Donckers, N., Verleysen, M., & Flandre, D. (2002). Multiplieur analogique en technologie SOI pour le décodage de turbo-codes. Proceedings du Colloque TAISA 2002, 69-73.
Pavanello, M. A., Der Agopian, P. G., Martino, J. A., & Flandre, D. (2002). Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Proceedings of the 5th European Workshop on Low Temperature Electronics (WOLTE 2002), 23-26. https://doi.org/10.1109/WOLTE.2002.1022444
Nève, A., Schettler, H., Ludwig, T., Hellner, G., & Flandre, D. (2002). Design of a Branch-Based 64-bit Carry-Select Adder in 0.18 µm Partially-Depleted SOI CMOS. Proceedings of the 2002 International Symposium on Low Power Electronics and Design (ISLPED ’02), 108-111. https://doi.org/10.1109/LPE.2002.146721
Article de journal
Adriaensen, S., Flandre, D., & Dessard, V. (2002). 25 to 300 degrees C ultra-low-power voltage reference compatible with standard SOICMOS process. Electronics Letters, 38(19), 1103-1104. https://doi.org/10.1049/el:20020768 (Original work published 2002)
Vanmackelberg, M., Raynaud, C., Faynot, O., Pelloie, J.-L., Tabone, C., Grouillet, A., Martin, F., Dambrine, G., Picheta, L., Mackowiak, E., Llinares, P., Sevenhans, J., Compagne, E., Fletcher, G., Flandre, D., Dessard, V., Vanhoenacker-Janvier, D., & Raskin, J.-P. (2002). 0.25 µm Fully-Depleted SOI MOSFET’s for RF mixed analog-digital circuits, including a comparison with Partially-Depleted devices for High Frequency noise parameters. Solid-State Electronics, 46(3), 379-386. https://doi.org/10.1016/S0038-1101(01)00120-4 (Original work published 2002)
Pavanello, M. A., Flandre, D., & Martino, J. A. (2002). Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, 46(8), 1215-1225. https://doi.org/10.1016/S0038-1101(02)00020-5 (Original work published 2002)
Pavanello, M., Der Agopian, P., Martino, J., & Flandre, D. (2002). Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, 12(3), 23-26. (Original work published 2002)
Sanchez, F., Flandre, D., Ortiz-Conde, A., Cerdeira, A., Estrada, M., & Liou, J. (2002). A method to extract mobility degradation and total series resistance of fully-depleted SOI MOSFETs. IEEE Transactions on Electron Devices, 49(1), 82-88. https://doi.org/10.1109/16.974753 (Original work published 2002)
Adriaensen, S., & Flandre, D. (2002). Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications. Solid-State Electronics, 46(9), 1339-1343. https://doi.org/10.1016/S0038-1101(02)00069-2 (Original work published 2002)
Cerdeira, A., Flandre, D., Estrada, M., Quintero, R., Ortiz-Conde, A., & Sanchez, F. (2002). New method for determination of harmonic distortion in SOI FD transistors. Solid-State Electronics, 46(1), 103-108. https://doi.org/10.1016/S0038-1101(01)00258-1 (Original work published 2002)
Dessard, V., Flandre, D., Iniguez, B., & Adriaensen, S. (2002). SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250 degrees C. IEEE Transactions on Electron Devices, 49(7), 1289-1295. https://doi.org/10.1109/TED.2002.1013288 (Original work published 2002)
Rudenko, T., Flandre, D., Kilchytska, V., Colinge, J.-P., & Dessard, V. (2002). On the high-temperature subthreshold slope of thin-film SOI MOSFETs. IEEE Electron Device Letters, 23(3), 148-150. https://doi.org/10.1109/55.988820 (Original work published 2002)
Quevy, E., Flandre, D., Parvais, B., Raskin, J.-P., Buchaillot, L., & Collard, D. (2002). A modified Bosch-type process for precise surface micromachining of polysilicon. Journal of Micromechanics and Microengineering, 12(3), 328-333. https://doi.org/10.1088/0960-1317/12/3/320 (Original work published 2002)
Chapitre de livre
Nève de Mévergnies, A., & Flandre, D. (2002). Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. In Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes (ed.), Soc Design Methodologies - IFIP TC10/WG 10.5 - Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC′01) December 3-5, 2001, Montpellier, France (p. p. 169-180). Kluwer Academic Publishers.
Flandre, D., Raskin, J.-P., & Vanhoenacker-Janvier, D. (2002). SOI CMOS Transistors for RF and Microwave Applications. In Deen M. Jamal et Fjeldly Tor A (eds.) (ed.), CMOS RF modeling, characterization and applications (p. p. 273-362). Word Scientific Publishing Co.
Brevet
Flandre, D., Pampin, R., Moreno Hagelsieb, L., Bourgeois, D., Remacle, J., & Lobert, P. E. (2002). Method and device for high sensitivity detection of the presence of DNA and other probes.
Nève, A., Raskin, J.-P., & Flandre, D. (2002). Fabrication method of semiconductor devices (Patent No. PCT/BE02/00043).
Papier de conférence
Quévy, E., Galayko, D., Legrand, B., Renaux, C., Combi, C., Flandre, D., Buchaillot, L., Collard, D., Vigna, B., & Kaiser, A. (2001). IF MEMS Filters for Mobile Communication. Proceedings of the 8th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA’01), 733-736.
Nève de Mévergnies, A., Dessard, V., Delatte, P., Brodeoux, V., Iniguez, B., Rauly, E., & Flandre, D. (2001). Improvement of sub 0.25 µm fully-depleted SOI CMOS analog performance by thinning the Si film. Electrochemical Society. Proceedings, 2001(3), 271-276. (Original work published 2001)
Afzalian, A., Delatte, P., Legat, J.-D., & Flandre, D. (2001). Bulk vs SOI CMOS APS optimal design for low power low voltage applications. Proceeding of ECCTD′01, p. II.53-II.56.
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). Analog circuit design using graded-channel SOI nMOSFETs. Proceedings of the 14th Symposium on Integrated Circuits and System Design (SBCCI′2001), 130-135.
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). Improved current mirror output performance by using graded-channel SOI nMOSFETs. Proceedings of the XVI SBMicro, International Conference on Microelectronics and Packaging, 12-16.
Dessard, V., Adriaensen, S., & Flandre, D. (2001). SOI n-MOSFET low-frequency noise from full to partial depletion: measurements, modeling and implications for analog designs. Proceedings of the 2001 IEEE International SOI Conference. 2001 IEEE International SOI Conference, Durango(USA).
Iniguez, B., Raskin, J.-P., Simon, P., Flandre, D., & Segura, J. (2001). Analysis and future trends of Iddq testing for silicon on insulator CMOS ICs. Proceedings of the 2001 IEEE International Workshop on Current and Defect Based Testing (DBI′2001), 40-44.
Levacq, D., Vancaillie, L., & Flandre, D. (2001). Top-down design of an UHF (433 MHz) fully integrated low-voltage, low-power SOI/CMOS voltage controlled oscillator. Proceedings of the 9th URSI Forum, 39.
Bellodi, M., Iniguez, B., Flandre, D., & Martino, J. A. (2001). Modelling of the leakage drain current in accumulation-mode SOI pMOSFETs for high-temperature applications. Electrochemical Society. Proceedings, 2001(3), 233-238. (Original work published 2001)
Cerdeira, A., Quintero, R., Estrada, M., Flandre, D., Ortiz-Conde, A., & Garcia Sanchez, F. J. (2001). An Efficient and Accurate Procedure to Evaluate Distortion in SOI FD MOSFET. Proceedings of the 2001 International Semiconductor Device Research Symposium, 477-478. https://doi.org/10.1109/ISDRS.2001.984549
Afzalian, A., Delatte, P., Legat, J.-D., & Flandre, D. (2001). Comparison of Bulk vs SOI for low power low voltage CMOS imager. Proceedings of the 2001 IEEE International SOI Conference, p. 133-134. https://doi.org/10.1109/SOIC.2001.958022
Rudenko, T., Kilchytska, V., Flandre, D., & Dessard, V. (2001). High Temperature Characterization of Carrier Generation in SOI MOS Devices Using Gated-Diode Technique. Proceedings of HITEN′2001 - International Conference on High Temperature Electronic. HITEN′2001 - International Conference on High Temperature Electronic, Oslo (Norway).
Vandooren, A., Cristoloveanu, S., Colinge, J.-P., & Flandre, D. (2001). Performance of double-gate SOI NMOSFETs at low temperature. Proceedings of the 2001 Electrochemical Society Conference, 427-432.
Iniguez, B., Raskin, J.-P., Demeûs, L., Nève de Mévergnies, A., Goffioul, M., Simon, P., Vanhoenacker-Janvier, D., & Flandre, D. (2001). A new fully-depleted SOI MOSFET macro-model valid from DC to RF. Electrochemical Society. Proceedings, 3, 193-198. (Original work published 2001)
Dessard, V., Adriaensen, S., & Flandre, D. (2001). Ultra-Low Power High-Temperature Voltage Reference Using Standard SOI CMOS Process. Proceedings of HITEN′2001 - International Conference on High Temperature Electronic. HITEN′2001 - International Conference on High Temperature Electronic, Oslo (Norway).
Picun, G., & Flandre, D. (2001). Characterization of thin-film SOI split-drain MOS transistors as magnetic sensors. Electrochemical Society. Proceedings, 2001(3), 289-294. (Original work published 2001)
Iniguez, B., Rauly, E., & Flandre, D. (2001). Potential of surface accumulation mode for deep-submicron fully-depleted SOI CMOS technologies. Electrochemical Society. Proceedings, 2001(3), 251-258. (Original work published 2001)
Quévy, E., Renaux, C., Buchaillot, L., Flandre, D., & Collard, D. (2001). MEMS for mobile communication. Proceedings of the 13th European Microelectronics and Packaging Conference and Exhibition (IMAPS’01), 129-134.
Ortiz-Conde, A., Garcia Sanchez, F. J., Cerdeira, A., Estrada, M., Flandre, D., & Liou, J. J. (2001). A procedure to extract mobility degradation, series resistance and threshold voltage of SOI MOSFETs in the saturation region. In Bing-Zong Li, Guo-Ping Ru, Xin-Ping Qu, Paul Yu, Hiroshi Iwai (ed.), Proceedings of the 6th International conference on solid-state and integrated circuit technology 2001 (pp. 887-890). IEEE Press. https://doi.org/10.1109/ICSICT.2001.982037
Nève de Mévergnies, A., & Flandre, D. (2001). Branch-Based Logic for High Performance Carry-Select Adders in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. Proceedings of PATMOS 2001, 8.
Laconte, J., Akheyar, A., Parvais, B., Afzalian, A., Dupont, C., Remus, V., Raskin, J.-P., & Flandre, D. (2001). Co-intégration de nouvelles techniques de micro-fabrication et du procédé CMOS/SOI standard en vue de réaliser des microsystèmes. Les MEMS : quelles compétences pour quels secteurs en Wallonie ?, Casteau Resort Hotel, Mons (Belgium).
Neve, A., Dessard, V., Delatte, P., Brodeoux, V., Iniguez, B., Rauly, E., & Flandre, D. (2001). Improvement of sub-0.25 mu m fully-depleted SOI CMOS analog performance by thinning the Si film. In Cristoloveanu, S.; Hemment, P.L.F.; Izumi, K.T.; Celler, G.K.; Assaderaghi, F.; Kim, Y-W; (ed.), Silicon-on-Insulator Technology and Devices X. Proceedings of the TenthInternational Symposium (Electrochemical Society Proceedings Vol.2001-3) (pp. 271-276). Electrochem. soc.
Picun, G., Demeûs, L., & Flandre, D. (2001). Charge injection characterization of thin-film SOI MOS transistors at high temperature. Electrochemical Society. Proceedings, 115-120.
Iniguez, B., Raskin, J.-P., Simon, P., Flandre, D., & Segura, J. (2001). Leakage components in fully-depleted SOI CMOS technology: implications on IDDQ testing. 2001 IEEE International Workshop on Defect Based Testing (DBT 2001), Marina del Rey, Los Angeles (USA).
Picun, G., Demeus, L., & Flandre, D. (2001). Charge injection characterization of thin-film SOI MOS transistors at high temperature. In Cristoloveanu, S.; Hemment, P.L.F.; Izumi, K.T.; Celler, G.K.; Assaderaghi, F.; Kim, Y-W; (ed.), Silicon-on-Insulator Technology and Devices X. Proceedings of the TenthInternational Symposium (Electrochemical Society Proceedings Vol.2001-3) (pp. 115-120). Electrochem. soc.
Laconte, J., Akheyar, A., Flandre, D., & Raskin, J.-P. (2001). Microsystems in SOI Technology. Electralis 2001, THe Campus, Liège (Belgium).
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). High performance current mirrors using graded-channel SOI NMOSFETS. Proceedings of the 10th International Symposium of the Electrochemical Society, 319-324.
Neve, A., Flandre, D., & Quisquater, J.-J. (2001). Smart Card Circuits in SOI Technology. Proceedings of the 2000 IEEE International SOI Conference, 48-49.
Adriaensen, S., Dessard, V., & Flandre, D. (2001). Analysis and Potential of the Bipolar- and Hybrid-Mode Thin-Film SOI MOSFETs for High-Temperature Applications. Proceedings of HITEN′2001 - International Conference on High Temperature Electronic, 74-78.
Flandre, D., Adriaensen, S., Akheyar, A., Demeûs, L., Delatte, P., Dessard, V., Iniguez, B., Nève, A., Laconte, J., Picun, G., Rauly, E., Renaux, C., Dehan, M., Parvais, B., Vanhoenacker-Janvier, D., & Raskin, J.-P. (2001). Sensors implementations in Silicon-on-Insulator CMOS compatible technology for micropower, radio-frequency or high-temperature applications. Proceedings du Colloque Micro/nano: quels défis pour l’industrie ? Published. Colloque Micro/nano: quels défis pour l’industrie ?, Louvain-la-Neuve (Belgium).
Flandre, D. (2001). High-Temperature Analog/Digital SOI processes and components. Proceedings of the Journées électroniques « haute temperature ». Journées électroniques « haute temperature », Lyon (France).
Delatte, P., Demeûs, L., Dessard, V., Picun, G., & Flandre, D. (2001). From BULK to SOI : A designer point of view. Proceedings of the Workshop on Status and Perspectives of SOI-Technologies and -Applications. Workshop on Status and Perspectives of SOI-Technologies and -Applications, Munich (Germany).
Flandre, D., Adriaensen, S., Akheyar, A., Crahay, A., Demeus, L., Delatte, P., Dessard, V., Iniguez, B., Neve, A., Katschmarskyj, B., Loumaye, P., Laconte, J., Martinez, I., Picun, G., Rauly, E., Renaux, C., Spote, D., Zitout, M., Dehan, M., et al. (2001). Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems. Solid-State Electronics, 45(4), 541-549. https://doi.org/10.1016/S0038-1101(01)00084-3 (Original work published 2001)
Bellodi, M., Iniguez, B., Flandre, D., & Martino, J. A. (2001). A simple leakage drain current model for accumulation-mode SOI nMOSFETs operating up to 300°C. In Patrick Verdonck, Carlos Alberto dos Reis Filho, José Camargo da Costa (ed.), Proceedings of the XVI SBMicro, International Conference on Microelectronics and Packaging (pp. 185-188).
Iniguez, B., Raskin, J.-P., Simon, P., Flandre, D., & Segura, J. (2001). Testing SOI CMOS IC’s with Parametric Testing Methods: a Fundamental Analysis. Proceedings of the XVI Conference on Design of Circuits and Integrated Systems (DCIS 2001), 636-640.
Nève de Mévergnies, A., & Flandre, D. (2001). Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. Proceedings of the 11th IFIP International Conference on very large Scale Integration (VLSI - SOC 2001), 269-272.
Iniguez, B., Rauly, E., & Flandre, D. (2001). Potential of surface accumulation mode for deep-submicron fully-depleted SOI CMOS technologies. In Cristoloveanu, S.; Hemment, P.L.F.; Izumi, K.T.; Celler, G.K.; Assaderaghi, F.; Kim, Y-W; (ed.), Silicon-on-Insulator Technology and Devices X. Proceedings of the TenthInternational Symposium (Electrochemical Society Proceedings Vol.2001-3) (pp. 251-258). Electrochem. soc.
Article de journal
Vandooren, A., Flandre, D., Cristoloveanu, S., & Colinge, J.-P. (2001). Hall effect measurements in double-gate SOI MOSFETs. Solid-State Electronics, 45(10), 1793-1798. https://doi.org/10.1016/S0038-1101(01)00207-6 (Original work published 2001)
Flandre, D., Raskin, J.-P., & Vanhoenacker-Janvier, D. (2001). SOI CMOS transistors for RF and microwave applications. International Journal of High Speed Electronics, 11(4), 1159-1248. https://doi.org/10.1142/S0129156401001076 (Original work published 2001)
Iniguez, B., Flandre, D., Raskin, J.-P., Demeus, L., Neve, A., Vanhoenacker-Janvier, D., Simon, P., & Goffioul, M. (2001). Deep-submicrometer DC-to-RF SOI MOSFET macro-model. IEEE Transactions on Electron Devices, 48(9), 1981-1988. https://doi.org/10.1109/16.944186 (Original work published 2001)
Demeus, L., Flandre, D., Dessard, V., Viviani, A., & Andriaensen, S. (2001). Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications. IEEE Transactions on Industrial Electronics, 48(2), 272-280. https://doi.org/10.1109/41.915405 (Original work published 2001)
Rauly, E., Flandre, D., & Iniguez, B. (2001). Investigation of deep submicron single and double gate SOI MOSFETs in accumulation mode for enhanced performance. Electrochemical and Solid-State Letters, 4(3), G28-G30. https://doi.org/10.1149/1.1347225 (Original work published 2001)
Raskin, J.-P., Laconte, P., Akheyar, A., Adriaensen, S., Nève, A., Martinez, I., Dehan, M., Parvais, B., Vanhoenacker-Janvier, D., Demeûs, L., Delatte, P., Dessard, V., & Flandre, D. (2001). Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems. Belgian Journal of Electronics & communications, 2, 53-68. (Original work published 2001)
Vandooren, A., Yuan, J.-G., Flandre, D., & Colinge, J.-P. (2001). Total-dose effects in double-gate-controlled NPN bipolar transistors. IEEE Transactions on Nuclear Science, 48(5), 1694-1699. https://doi.org/10.1109/23.960359 (Original work published 2011)
Brevet
Dessard, V., Flandre, D., & Adriaensen, S. (2001). Ultra Low Power Analog Basic Blocks.
Papier de conférence
Martinez, I., Delatte, P., & Flandre, D. (2000). Characterization, simulation and modelling of PLL under irradiation using HDL-A. Proceedings of IEEE BMAS-2000, 57-61.
Rauly, E., Iniguez, B., Flandre, D., & Raynaud, C. (2000). Investigation of single and double gate SOI MOSFETs in Accumulation Mode for enhanced performances and reduced technological drawbacks. In Lane, W.A.; Crean, G.M.; McCabe, F.A.; Grunbacher, H.; (ed.), ESSDERC 2000. Proceedings of the 30th European Solid-State DeviceResearch Conference (pp. 540-543). Frontier group.
Raynaud, C., Flandre, D., Dessard, V., Vanhoenacker-Janvier, D., & Raskin, J.-P. (2000). 70 GHz fmax fully-depleted SOI MOSFET’s for low-power wireless applications. Proceedings of the 30th European Microwave Week GaAS 2000, 268-271.
Bellodi, M., Iniguez, B., Flandre, D., & Martino, J. A. (2000). Diodes model for the leakage drain current in enhancement-mode SOI nMOSFETs at 300°C. Proceedings of the International Conference on Microelectronics and Packaging. International Conference on Microelectronics and Packaging, Manaus (Brésil).
Martinez, I., Delatte, P., Berger, G., & Flandre, D. (2000). Characterization and high-level modeling of SOI ring oscillators under irradiation. Proceedings of the European Conference on Radiation Effects on Components and Systems (RADECS 2000), 205-208.
Sabadell, J., Celma, S., & Flandre, D. (2000). A 1.5 V SOI-CMOS transconductor for high frequencies. Proceedings of the EUROSOI 2000 Meeting on Silicon-on-Insulator Devices, Session 4, paper 2.
Pavanello, M. A., Martino, J. O., & Flandre, D. (2000). Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. Proceedings of the 3rd IEEE International Caracas Conference on devices, circuits and systems, D44.
Raskin, J.-P., Vanhoenacker-Janvier, D., Dehan, M., Goffioul, P., Simon, P., Iniguez, B., Renaux, C., & Flandre, D. (2000). SOI CMOS for Low-Voltage, Low-Power Microwave Applications. Proceedings of the EUROSOI 2000 Meeting on Silicon-on-Insulator Devices, 35-38.
Silveira, F., & Flandre, D. (2000). Analysis and design of a family of low-power class AB operational amplifiers. Proceedings of the International Conference on Microelectronics and Packaging, 94-98.
Flandre, D., & Adriaensen, S. (2000). Optimization of the operation of the thin-film SOI lateral bipolar transistor for high-temperature applications. Proceedings of the Fifth International High temperature Conference. Fifth International High temperature Conference, Albuquerque (USA).
Sabadell, J., Celma, S., Flandre, D., Aldea, C., & Martinez, P. A. (2000). SOI solutions for HF applications. Proceedings of the 15th Conference on Design of Circuits and Integrated Systems. 15th Conference on Design of Circuits and Integrated Systems, Montpellier (France).
Demeûs, L., Delatte, P., Dessard, V., Adriaensen, S., Renaux, C., & Flandre, D. (2000). A review of fully-depleted SOI CMOS technology for microsystems. Proceedings of the 3rd International Conference on Micro Materials, 69-72.
Flandre, D. (2000). Fully-depleted SOI-CMOS technology for heterogeneous micropower and high-temperature microsystems. Proceedings of the EUROSOI 2000 Meeting on Silicon-on-Insulator Devices, session 1, paper 1.
Nève, A., Flandre, D., & Quisquater, J.-J. (2000). Smart Card Circuits in SOI Technology. Proceedings of the 2000 IEEE International SOI Conference, 48-49.
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Parasitic bipolar effects in graded-channel fully-depleted Silicon-on-Insulator nMOSFETs. Proceedings of the International Conference on Microelectronics and Packaging, 97-102.
Demeûs, L., Delatte, P., Dessard, V., & Flandre, D. (2000). Innovative SOI circuit design for extreme applications. Proceedings of the EUROSOI 2000 Meeting on Silicon-on-Insulator Devices, Session 4, paper 5.
Rudenko, T., Kilchytska, V., Colinge, J.-P., & Flandre, D. (2000). Physical analysis of the high-temperature subthreshold slope in SOI MOSFETs. Proceedings of the 2000 IEEE International SOI Conference, 30-32.
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. Proceedings of the International Conference on Microelectronics and Packaging, 67-71.
Dessard, V., Adriaensen, S., & Flandre, D. (2000). Low-Noise High-Temperature SOI Analog Circuits. Proceedings of the 3rd International Workshop “Progress in Semiconductor-on-Insulator Structures and Devices Operating at Extreme Conditions”. 3rd International Workshop “Progress in Semiconductor-on-Insulator Structures and Devices Operating at Extreme Conditions”, Kyiv (Ukraine).
Bellodi, M., Iniguez, B., Flandre, D., Raynaud, C., & Martino, J. A. (2000). Study of the deep-submicron SOI MOSFET leakage current behavior at high temperatures. Proceedings of the International Conference on Microelectronics and Packaging, 304-307.
Delatte, P., Brodéoux, V., Lorent, Ph., & Flandre, D. (2000). Comparison of 0.25 µm Bulk, PD and FD SOI CMOS implementations of a Low-Voltage Low-Power Programmable DLL for Linear Delay Generation. Proceedings of the 2000 IEEE International SOI Conference, 92-93.
Flandre, D. (2000). Process alternative: SOI for heterogeneous systems. Microelectronic Engineering, 54(1-2), 49-62. (Original work published 2000)
Dessard, V., Adriaensen, S., & Flandre, D. (2000). High-temperature, constant gain, compact transistor-only, instrumentation fully differential preamplifier. Proceedings of the Fifth International High temperature Conference. Fifth International High temperature Conference, Albuquerque (USA).
Article de journal
Pavanello, M. A., Flandre, D., Martino, J. A., & Dessard, V. (2000). Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, 44(7), 1219-1222. https://doi.org/10.1016/S0038-1101(00)00034-4 (Original work published 2000)
Pavanello, M. A., Flandre, D., Martino, J. A., & Dessard, V. (2000). An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, 3(1), 50-52. https://doi.org/10.1149/1.1390955 (Original work published 2000)
Flandre, D. (2000). Process alternative: SOI for heterogeneous systems. Microelectronic Engineering, 54, 49-62. https://doi.org/10.1016/S0167-9317(00)80058-1 (Original work published 2000)
Pavanello, M. A., Flandre, D., & Martino, J. A. (2000). Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44(6), 917-922. https://doi.org/10.1016/S0038-1101(00)00032-0 (Original work published 2000)
Chapitre de livre
Flandre, D. (2000). Part 1: Design of low-voltage low-power CMOS analog building blocks and OTAs using EKV modelling and gm/ID methodology in bulk and SOI technologies. In Low power techniques and neural applications in microelectronics (p. p. 3-99). Ed. by J. Oliver.
Brevet
Dessard, V., & Flandre, D. (2000). Differential amplifier with gain substantially independent of temperature (Patent No. 00110707.7–2215).
Papier de conférence
Nève, A., Flandre, D., & Quisquater, J.-J. (1999). Feasibility of the smart card in Silicon-on-Insultaor (SOI) technology. Proceedings of the USENIX workshop on smartcard technology, 1-7.
Flandre, D., Legat, J.-D., & Delatte, P. (1999). Oscillateurs en Anneau CMOS SOI à Basse Tension d’Alimentation. Proc. of 2èmes journées francophones d’études faible consommation FTFC′99, p. 66-69.
Adriaensen, S., Dessard, V., Delatte, P., Querol, J. R., Flandre, D., & Richter, S. (1999). High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures. Proceedings of HITEN 1999, 79-82. https://doi.org/10.1109/HITEN.1999.827467
Iniguez, B., Demeûs, L., Nève, A., Flandre, D., D’Hayer, S., Simon, P., Vanhoenacker-Janvier, D., & Raynaud, C. (1999). Deep-submicron DC to RF SOI MOSFET characterization and modelling. Proceedings of the 1999 International Semiconductor device research Symposium, 441-444.
Flandre, D., Legat, J.-D., & Delatte, P. (1999). PLL Jitter Behavioral Modeling and Simulation using HDL-A. Proc. of BMAS′99, p. 6 pages.
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (1999). The graded-channel SOI MOSFET to alleviate the parasitic bipolar effects and improve the output characteristics. Proceedings of the Electrochemical Society 1999. Electrochemical Society 1999, Seattle (USA).
Demeûs, L., Delatte, P., Dessard, V., Adriaensen, S., Renaux, C., & Flandre, D. (1999). The art of high-temperature FD-SOI CMOS. Proceedings of HITEN 1999, 97-99. https://doi.org/10.1109/HITEN.1999.827472
Flandre, D., Dessard, V., Demeûs, L., Viviani, A., & Colinge, J.-P. (1999). Fully-depleted SOI CMOS circuits for operation above 250°C. Proceedings of the 1999 NASA/JPL conference on Electronics for Extreme Environments. 1999 NASA/JPL conference on Electronics for Extreme Environments, Pasadena (USA).
Adriaensen, S., Dessard, V., & Flandre, D. (1999). A bandgap circuit operating up to 300°C using lateral bipolar transistors in thin-film CMOS-SOI technology. Proceedings of HITEN 1999, 49-52.
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (1999). Graded-channel SOI NMOSFET and its potential to analog applications. Proceedings of the International Conference on Microelectronics and Packaging, 105-109.
Renaux, C., Scheuren, V., & Flandre, D. (1999). New experiments on the electrodeposition of iron in porous silicon. Proceedings of the 10th Workshop on dielectrics in microelectronics, 203-204.
Iniguez, B., Nève, A., Flandre, D., & Raynaud, C. (1999). Unified deep-submicron fully-depleted SOI MOSFET modeling for circuit simulation. Proceedings of the XIV Congreso de Diseño de Circuitos Integrados, 427-432.
Colinge, J.-P., Vandooren, A., & Flandre, D. (1999). Gate-All-Around Technology for Harsh Environment Applications. Proceedings of the 1999 NASA/JPL conference on Electronics for Extreme Environments. 1999 NASA/JPL conference on Electronics for Extreme Environments, Pasadena (USA).
Article de journal
Flandre, D., Colinge, JP., Chen, J., De Ceuster, D., Eggermont, JP., Ferreira, L., Gentinne, B., Jespers, PGA., Viviani, A., Gillon, R., Raskin, J.-P., Vander Vorst, A., Vanhoenacker-Janvier, D., & Silveira, F. (1999). Fully-depleted SOI CMOS technology for low-voltage, low-power mixed digital/analog/microwave circuits. Analog Integrated Circuits and Signal Processing, 21(3), 213-228. https://doi.org/10.1023/A:1008321919587 (Original work published 1999)
Viviani, A., Jespers, P., & Flandre, D. (1999). High-temperature sigma-delta modulator in thin-film fully-depleted SOI technology. Electronics Letters, 35(9), 749-751. https://doi.org/10.1049/el:19990513 (Original work published 1999)
Vandooren, A., Flandre, D., & Colinge, JP. (1999). Gate-all-around OTA’s for rad-hard and high-temperature analog applications. IEEE Transactions on Nuclear Science, 46(4), 1242-1249. https://doi.org/10.1109/23.785739 (Original work published 1999)
Ernst, T., Flandre, D., Vandooren, A., Cristoloveanu, S., & Colinge, JP. (1999). Carrier lifetime extraction in fully depleted dual-gate SOI devices. IEEE Electron Device Letters, 20(5), 209-211. https://doi.org/10.1109/55.761017 (Original work published 1999)
Iniguez, B., Flandre, D., Gentinne, B., & Dessard, V. (1999). A physically-based C-infinity-continuous model for accumulation-mode SOI pMOSFET’s. IEEE Transactions on Electron Devices, 46(12), 2295-2303. https://doi.org/10.1109/16.808063 (Original work published 1999)
Renaux, C., Scheuren, V., & Flandre, D. (1999). New experiments on the electrodeposition of iron in porous silicon. Microelectronics Reliability, 40(4-5), 877-879. https://doi.org/10.1016/S0026-2714(99)00331-5 (Original work published 2000)
Article de journal
Eggermont, J.-P., Flandre, D., Raskin, J.-P., & Colinge, J.-P. (1998). Potential and modeling of 1-mu m SOI CMOS operational transconductance amplifiers for applications up to 1 GHz. IEEE Journal of Solid State Circuits, 33(4), 640-643. https://doi.org/10.1109/4.663571 (Original work published 1998)
Losantos, P., Cane, C., Flandre, D., & Eggermont, J.-P. (1998). Magnetic-field sensor based on a thin-film SOI transistor. Sensors and Actuators A: Physical : an international journal devoted to research and development of physical and chemical transducers, 67(1-3), 96-101. (Original work published 1998)
Flandre, D. (1998). SOI CMOS technology for high-temperature microsystems. MST News, 2, 18-20. (Original work published 1998)
Flandre, D. (1998). Silicon-on-insulator technology for high temperature metal oxide semiconductor devices and circuits. Materials Science and Engineering B: Solid-State Materials for Advanced Technology, 29(1-3), 7-12. https://doi.org/10.1016/0921-5107(94)04018-Y (Original work published 2000)
Gillon, R., Colinge, J.-P., Flandre, D., Raskin, J.-P., & Vanhoenacker-Janvier, D. (1998). Silicon-on-Insulator for RF and microwave low-power applications. Microwave engineering Europe, 49-54. (Original work published 1998)
Papier de conférence
Vandooren, A., Flandre, D., Cristoloveanu, S., & Colinge, J.-P. (1998). Edge effects characterization in gate-all-around SOI MOSFETs. Proceedings of the IEEE International SOI Conference, 1998, 75-76. https://doi.org/10.1109/SOI.1998.723118
Eggermont, J.-P., Dessard, V., Vandooren, A., Flandre, D., & Colinge, J.-P. (1998). SOI current and voltage reference sources for applications up to 300°C. Proceedings of the Fourth International High Temperature Conference (HITEC 1998), 55-59. https://doi.org/10.1109/HITEC.1998.676761
Demeûs, L., Chen, J., Eggermont, J.-P., Gillon, R., Raskin, J.-P., Vanhoenacker-Janvier, D., & Flandre, D. (1998). Advanced SOI CMOS technology for RF applications. Proceedings of the URSI International Symposium on Signals, Systems, and Electronics, 1998 (ISSSE 1998), 134-139. https://doi.org/10.1109/ISSSE.1998.738053
Flandre, D., & Vanhoenacker-Janvier, D. (1998). Thin-film fully-depleted SOI CMOS technology devices and circuits for LVLP analog/digital/microwave applications. Proceedings of the International Semiconductor Conference, 1998 (CAS 1998), 115-124.
Flandre, D., Demeûs, L., Dessard, V., Viviani, A., Gentinne, B., & Eggermont, J.-P. (1998). Design and application of SOI CMOS OTAs for high-temperature applications. Proceedings of the 24th European Solid-State Circuits Conference 1998 (ESSCIRC 1998), 404-407. https://doi.org/10.1109/ESSCIR.1998.186294
Gillon, R., Colinge, J.-P., Flandre, D., Raskin, J.-P., & Vanhoenacker-Janvier, D. (1998). Silicon-on-insulator for RF and microwave low-power applications. Proceedings of the Microwave Eng. Workshop on New technologies for RF devices, Session 2, paper 3.
Demeûs, L., Viviani, A., & Flandre, D. (1998). High-temperature analog instrumentation system in thin-film fully-depleted SOI CMOS technology. Proceedings of the Fourth International High Temperature Conference (HITEC 1998), 51-54. https://doi.org/10.1109/HITEC.1998.676760
Dessard, V., & Flandre, D. (1998). Low Frequency Noise Measurements at Elevated Temperatures on Thin-Film SOI n-MOSFET. 28th European Solid-State Device Research Conference, Bordeaux (France).
Dessard, V., Eggermont, J.-P., & Flandre, D. (1998). Thin-film SOI n-MOSFET low-frequency noise measurements at elevated temperatures. Proceedings of the Engineering Foundation Conference on High Temperature Electronic Materials, Devices and Sensors. Engineering Foundation Conference on High Temperature Electronic Materials, Devices and Sensors, San Diego (USA). https://doi.org/10.1109/HTEMDS.1998.730657
Ernst, T., Cristoloveanu, S., Vandooren, A., Colinge, J.-P., & Flandre, D. (1998). Recombination current and carrier lifetime extraction in dual-gate fully depleted SOI devices. Proceedings of the 28th European Solid-State Research Conference (ESSDERC 1998). 28th European Solid-State Research Conference (ESSDERC 1998), Bordeaux (France).
Dessard, V., Demeûs, L., Viviani, A., Adriaensen, S., Binard, C., Crahay, A., Renaux, C., Loumaye, P., Spote, D., Flandre, D., & Katschmarskyj, B. (1998). Integrated sensors and electronic circuits in SOI technology for high-temperature applications. Forum Microsystems, Liège (Belgium).
Article de journal
Francis, P., Colinge, JP., & Flandre, D. (1997). Comparison of self-heating effect in GAA and SOI mosfets. Microelectronics Reliability, 37(1), 61-75. https://doi.org/10.1016/0026-2714(96)00239-9 (Original work published 1997)
Eggermont, J.-P., Flandre, D., Raskin, J.-P., & Colinge, J.-P. (1997). Potential and Modeling of 1 µm - 1 GHz SOI CMOS OTAs. Electronics Letters, 33(9), 774-775 (April). (Original work published 1997)
Chen, J., Colinge, J.-P., Flandre, D., Gillon, R., Raskin, J.-P., & Vanhoenacker-Janvier, D. (1997). Comparison of TiSi2, CoSi2, and NiSi for thin-film silicon-on-insulator applications. Journal of the Electrochemical Society, 144(7), 2437-2442. https://doi.org/10.1149/1.1837833 (Original work published 1997)
Gentinne, B., Eggermont, J.-P., Flandre, D., & Colinge, J.-P. (1997). Fully depleted SOI-CMOS technology for high temperature IC applications. Materials Science and Engineering B: Solid-State Materials for Advanced Technology, 46(1-3), 1-7. https://doi.org/10.1016/S0921-5107(96)01921-6 (Original work published 1997)
Raskin, J.-P., Viviani, A., Flandre, D., & Colinge, J.-P. (1997). Substrate crosstalk reduction using SOI technology. IEEE Transactions on Electron Devices, 44(12), 2252-2261. https://doi.org/10.1109/16.644646 (Original work published 1997)
Flandre, D. (1997). High-temperature electronics applications of SOI CMOS technology. Revue HF Electronics/Communications, 4, 17-30. (Original work published 1997)
Flandre, D., Viviani, A., Eggermont, J.-P., Gentinne, B., & Jespers, P. (1997). Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. IEEE Journal of Solid State Circuits, 32(7), 1006-1012. https://doi.org/10.1109/4.597291 (Original work published 1997)
Iniguez, B., Tambani, M., Dessard, V., & Flandre, D. (1997). Unified 1/f noise SOI MOSFET modelling for circuit simulation. Electronics Letters, 33(21), 1781-1782. https://doi.org/10.1049/el:19971196 (Original work published 1997)
Eggermont, J.-P., Flandre, D., Raskin, J.-P., & Colinge, J.-P. (1997). Potential and modelling of 1 mu m 1GHz SOI CMOS OTAs. Electronics Letters, 33(9), 774-775. https://doi.org/10.1049/el:19970517 (Original work published 1997)
Papier de conférence
Jespers, P., Colinge, J.-P., & Flandre, D. (1997). Low-voltage low-power potential of SOI (Silicon on Insulator). Proceedings FTFC 1997, 1-15.
Flandre, D. (1997). Circuits for high-temperature electronics. Proceedings of HITEN 1997, 53-61.
Dessard, V., & Flandre, D. (1997). High-temperature low-frequency noise measurements in thin-film SOI n-MOSFETs. Proceedings of HITEN 1997, 139-144.
Flandre, D., Viviani, A., Eggermont, J.-P., Gentinne, B., & Jespers, P. (1997). Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. Proceedings of the 22nd European Solid-State Circuits Conference (ESSCIRC 1996). 22nd European Solid-State Circuits Conference (ESSCIRC 1996), Neuchatel (Suisse).
Ferreira, L., Flandre, D., & Jespers, P. (1997). A method to extend the validity of quasi-static SOI MOSFET models. Proceedings OF PATMOS 1997, 225-233.
Vandooren, A., Eggermont, J.-P., & Flandre, D. (1997). High-temperature and ultra rad-hard GAA/SOI amplifiers. Proceedings of HITEN 1997, 319-323.
Sadabell, J., Flandre, D., Celma, S., & Martinez, P. A. (1997). Current-mode SOI technology based Tow-Thomas filter. Proceedings of the 4th International Workshop on Mixed design of Integrated Circuits and Systems (MIXDES 1997), 359-364.
Losantos, P., Cané, C., Flandre, D., & Eggermont, J.-P. (1997). MOS-bipolar magnetic field sensor on thin film SOI technology. Proceedings of EUROSENSORS XI, 271-274.
Losantos, P., Cane, C., Flandre, D., & Eggermont, J.-P. (1997). Magnetic-field sensor based on a thin-film SOI transistor. Sensors and Actuators A: Physical : an international journal devoted to research and development of physical and chemical transducers, 67(1-3), 96-101. https://doi.org/10.1016/S0924-4247(97)01771-8 (Original work published 1998)
Sabadell, J., Celma, S., Flandre, D., & Martinez, P. A. (1997). A continuous time biquad in SOI technology. Proceedings of the XII Congreso de Diseno de Circuitos Integrados, 65-70.
Demeûs, L., & Flandre, D. (1997). Comparison of charge injection in SOI and bulk MOS analog switches. Proceedings of the IEEE International SOI Conference, 1997, 104-105.
Marin, D., Escudero, J., Oliver, J., & Flandre, D. (1997). CONNAN: A computer-aided design tool based on sharing information for analog circuit sizing. Proceedings OF PATMOS 1997, 67-75.
Eggermont, J.-P., Dessard, V., Vandooren, A., Flandre, D., & Colinge, J.-P. (1997). SOI current and voltage reference sources for applications up to 300°C”. Proceedings of HITEN 1997. Conference HITEN 1997, Manchester (UK).
Chen, J., Colinge, J.-P., Flandre, D., Nguyen, B.-Y., Hegde, R., & Rai, R. (1997). Formation of TiN/CoSi2 barrier layer on thin-film SOI for high-temperature applications. Proceedings of HITEN 1997, 159-164.
Loukil, T., Dondon, P., Eggermont, J.-P., Dessard, V., Flandre, D., & Zardini, C. (1997). SOI MOSFETs capacitive pressure transducers for high-temperature applications. Proceedings of HITEN 1997, 231-235.
Iniguez, B., Gentinne, B., Dessard, V., & Flandre, D. (1997). CAD-compatible model for accumulation-mode (AM) SOI pMOSFETs. Proceedings of the IEEE International SOI Conference, 1997, 92-93.
Chen, J., Colinge, J.-P., Flandre, D., Gillon, R., Raskin, J.-P., & Vanhoenacker-Janvier, D. (1997). Investigation of salicide processes for thin-film SOI microwave applications. Proceedings of the 8th International Symposium on SOI technology and devices (ECS 1997), 98-103.
Vandooren, A., Francis, P., Flandre, D., & Colinge, J.-P. (1997). Performance of gamma-irradiated Gate-All-Around SOI MOS OTA amplifiers. Proceedings of the IEEE International SOI Conference, 1997, 62-63.
Papier de conférence
Russo, G. V., Caligiore, C., Lo Presti, D., Panebianco, S., Randazzo, N., Russo, M., Aiello, S., Belluomo, P., Reito, S., Flandre, D., & Viviani, A. (1996). CMOS analog ASICs full custom for nuclear physics applications. Proceedings of the 1st European workshop on Microelectronics education. Published. 1st European workshop on Microelectronics education, Grenoble (France).
Marin, D., Flandre, D., Carrabina, J., & Oliver, J. (1996). Aplicaciòn de la metodologìa gm/Id: Diseno de un detector de portadora para RF en tecnologìa SOI. Proceedings of the XI Congreso de Diseño de Circuitos Integrados. Published. XI Congreso de Diseño de Circuitos Integrados.
Flandre, D. (1996). High-temperature SOI MOS device processing. Proceedings of the HITEN TIG Meeting 1996. HITEN TIG Meeting 1996, Paris (France).
Flandre, D., Silveira, F., Eggermont, J.-P., Gentinne, B., Dessard, V., Viviani, A., Baldwin, D., Demeûs, L., & Jespers, P. (1996). Design automation of CMOS OTAs using symbolic analysis and gm/ID methodology. Proceedings of SMACD 1996. Published. SMACD 1996, Leuven (Belgium).
Dessard, V., Baldwin, D., Demeûs, L., Gentinne, B., & Flandre, D. (1996). SOI implementation of low-voltage and high-temperature MOSFET-C continuous-time filters. Proceedings of the IEEE International SOI Conference, 1996, 24-25. https://doi.org/10.1109/SOI.1996.552475
Dessard, V., Gentinne, B., & Flandre, D. (1996). Potential and design of MOSFET-C continuous-time filters in SOI technology. Proceedings of ESSCIRC′96, 416-419.
Colinge, J.-P., Chen, J., Flandre, D., Raskin, J.-P., Gillon, R., & Vanhoenacker-Janvier, D. (1996). A low-voltage, low-power microwave SOI MOSFET. Proceedings of the IEEE International SOI Conference, 1996, 128-129. https://doi.org/10.1109/SOI.1996.552527
Viviani, A., Flandre, D., & Jespers, P. (1996). A SOI-CMOS micro-power first-order Sigma-Delta modulator. Proceedings of the IEEE International SOI Conference, 1996, 110-111. https://doi.org/10.1109/SOI.1996.552518
Eggermont, J.-P., Flandre, D., & Colinge, J.-P. (1996). CMOS SOI magnetic field sensors for applications up to 300°C. Proceedings of the Third International High Temperature Conference, X3-X8.
Flandre, D., Viviani, A., Eggermont, J.-P., Gentinne, B., & Jespers, P. (1996). Design methodology for CMOS gain-boosted folded-cascode OTA with application to SOI technology. Proceedings of ESSCIRC′96, 320-323.
Gentinne, B., Flandre, D., Eggermont, J.-P., & Colinge, J.-P. (1996). High-temperature performances of a SOI CMOS gain-boosting OTA. Proceedings of the Third International High Temperature Conference, 113-118.
Bellodi, M., Martino, J. A., & Flandre, D. (1996). Introduction of the SOI MOSFET dimensions in the high-temperature leakage drain current model. Proceedings of the XI Congress of the Brazilian Microelectronics Society. Published. XI Congress of the Brazilian Microelectronics Society, Aguas de Sindoia (Brazil).
Article de journal
Silveira, F., Flandre, D., & Jespers, PGA. (1996). A g(m)/I-D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE Journal of Solid State Circuits, 31(9), 1314-1319. https://doi.org/10.1109/4.535416 (Original work published 1996)
Wainwright, S., Hall, S., & Flandre, D. (1996). The effect of series resistance on threshold voltage measurement techniques for fully depleted SOI MOSFETs. Solid-State Electronics, 39(1), 89-94. https://doi.org/10.1016/0038-1101(95)00120-I (Original work published 1996)
Flandre, D., Ferreira, L. F., Jespers, P., & Colinge, J.-P. (1996). Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits. Solid-State Electronics, 39(4), 455-460. https://doi.org/10.1016/0038-1101(95)00167-0 (Original work published 1996)
Deceuster, D., Flandre, D., Colinge, J.-P., & Cristoloveanu, S. (1996). Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors. Electronics Letters, 32(4), 278-279. https://doi.org/10.1049/el:19960252 (Original work published 1996)
Gentinne, B., Flandre, D., & Colinge, J.-P. (1996). Measurement and modeling of thin-film accumulation-mode SOI p-MOSFET intrinsic gate capacitances. Solid-State Electronics, 39(7), 1071-1078. https://doi.org/10.1016/0038-1101(95)00408-4 (Original work published 1996)
Gentinne, B., Flandre, D., Colinge, J.-P., & Vandewiele, F. (1996). Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures. Solid-State Electronics, 39(11), 1613-1619. https://doi.org/10.1016/0038-1101(96)00067-6 (Original work published 1996)
Bellodi, M., Martino, J. A., & Flandre, D. (1996). New empirical model for leakage drain current of SOI MOSFETs valid from room to high temperatures. Journal of Solid-State Devices and Circuits, 7-10. (Original work published 1996)
Iniguez, B., Ferreira, L., Gentinne, B., & Flandre, D. (1996). A physically-based C-infinity-continuous fully-depleted SOI MOSFET model for analog applications. IEEE Transactions on Electron Devices, 43(4), 568-575. https://doi.org/10.1109/16.485539 (Original work published 1996)
Eggermont, JP., Deceuster, D., Flandre, D., Gentinne, B., Jespers, PGA., & Colinge, JP. (1996). Design of SOI CMOS operational amplifiers for applications up to 300 degrees C. IEEE Journal of Solid State Circuits, 31(2), 179-186. https://doi.org/10.1109/4.487994 (Original work published 1996)
Papier de conférence
Flandre, D. (1995). Silicon-on-insulator Technology for High-temperature Metal-oxide-semiconductor Devices and Circuits. Materials Science and Engineering B: Solid-State Materials for Advanced Technology, 29(1-3), 7-12. (Original work published 1995)
Bellodi, M., Martino, J. A., & Flandre, D. (1995). New leakage drain current model for high-temperature SOI MOSFET. Proceedings of the X Congress of Brazilian Microelectronics Society, 557-563.
Eggermont, J.-P., Flandre, D., Gillon, R., & Colinge, J.-P. (1995). A 1-GHz operational transconductance amplifier in SOI technology. Proceedings of the IEEE International SOI Conference, 1995, 127-128. https://doi.org/10.1109/SOI.1995.526493
Gentinne, B., Dessard, V., Louveaux, S., Flandre, D., & Colinge, J.-P. (1995). A comparative study of non-linearities in bulk and SOI linear resistors based on 2- and 4-transistor structures. Proceedings of the IEEE International SOI Conference, 1995, 64-65. https://doi.org/10.1109/SOI.1995.526462
Raskin, J.-P., Viviani, A., Flandre, D., Colinge, J.-P., & Vanhoenacker-Janvier, D. (1995). Extended study of crosstalk in SOI-SIMOX substrates. Proceedings of the International Electron Devices Meeting 1995 (IEDM 1995), 713-716. https://doi.org/10.1109/IEDM.1995.499318
Silveira, F., Flandre, D., & Jespers, P. (1995). La tecnologia CMOS sobre SOI (Silicon-on-Insulator) para aplicaciones analògico-digitales da baja tensiòn y bajo consumo. Proceedings of the II Simposio Nacional de Microelectrònica de la Repùblica Argentina. Published. II Simposio Nacional de Microelectrònica de la Repùblica Argentina, Rosario (Argentina).
Francis, P., Flandre, D., Colinge, J.-P., & Van de Wiele, F. (1995). Comparison of self-heating in effects in GAA and SOI devices. Proceedings of the 25th ESSDERC Conference, 225-228.
Raskin, J.-P., Vanhoenacker-Janvier, D., Colinge, J.-P., & Flandre, D. (1995). Coupling effects in high-resistivity SIMOX substrates for VHF and microwave applications. Proceedings of the IEEE International SOI Conference, 1995, 62-63.
Wainwright, S. P., Hall, S., & Flandre, D. (1995). Accurate threshold voltage measurement for use with SOISPICE. Proceedings of the 25th ESSDERC Conference, 753-756.
Colinge, J.-P., Eggermont, J.-P., Flandre, D., Francis, P., & Jespers, P. (1995). Potential of SOI for analog and mixed analog-digital low-power applications. Proceedings of the IEEE International Solid-State Circuits Conference, 194-195. https://doi.org/10.1109/ISSCC.1995.535519
Riera, J., Carrabina, J., & Flandre, D. (1995). CMOS SOI&Bulk: Cell Level Comparison. Proceedings of X Congreso de Diseño de Circuitos Integrados, 20-23.
Article de journal
Flandre, D., & Jespers, P. (1995). Charge-sheet Modeling of Mos I-v Fundamental Nonlinearities in Mosfet-c Continuous-time Filters. Electronics Letters, 31(17), 1419-1420. https://doi.org/10.1049/el:19951016 (Original work published 1995)
Auberton-Hervé, A. J., Colinge, J.-P., & Flandre, D. (1995). High-temperature applications of SIMOX technology. HITEN News, 5. (Original work published 1995)
Francis, P., Flandre, D., & Colinge, J.-P. (1995). Theoretical Considerations for Sram Total-dose Hardening. IEEE Transactions on Nuclear Science, 42(2), 83-91. https://doi.org/10.1109/23.372136 (Original work published 1995)
Francis, P., Flandre, D., Terao, A., & Vandewiele, F. (1995). Moderate Inversion Model of Ultrathin Double-gate Nmos/soi Transistors. Solid-State Electronics, 38(1), 171-176. https://doi.org/10.1016/0038-1101(94)E0035-D (Original work published 1995)
Papier de conférence
Zaleski, A., Ioannou, D. E., Flandre, D., & Colinge, J.-P. (1994). Design and performance of a new flash EEPROM on SOI (SIMOX) substrates. Proceedings of the IEEE International SOI Conference, 1992. Published. IEEE International SOI Conference, 1994, Nantucket Island (USA). https://doi.org/10.1109/SOI.1994.514205
Flandre, D., Gentinne, B., Eggermont, J.-P., De Ceuster, D., Colinge, J.-P., & Jespers, P. (1994). CMOS on SOI operational amplifiers for application up to 300°C. Proceedings of the Second International High temperature Conference, II.
Flandre, D., & Colinge, J.-P. (1994). Status and trends of SOI. Proceedings of ESSCIRC′94, 18-27.
Flandre, D., Gentinne, B., Eggermont, J.-P., & Jespers, P. (1994). Design of thin-film fully-depleted SOI CMOS analog circuits significantly outperforming bulk implementations. Proceedings of the IEEE International SOI Conference, 1994, 99-100. https://doi.org/10.1109/SOI.1994.514265
Flandre, D. (1994). SOI technology for high-temperature MOS devices and circuits. Proceedings of EMRS 1994 spring Meeting, E-VIII.
Flandre, D. (1994). High-temperature operation of Silicon-on-Insulator MOS devices and circuits. Proceedings of Hochtemperaturelktronik, II.
Flandre, D., & Colinge, J.-P. (1994). High-temperature SOI technology. Proceedings of the IX Brazilian Microelectronics Society Congress, 777-786.
Article de journal
Colinge, J.-P., Flandre, D., & Vandewiele, F. (1994). Subthreshold Slope of Long-channel, Accumulation-mode P-channel Soi Mosfets. Solid-State Electronics, 37(2), 289-294. https://doi.org/10.1016/0038-1101(94)90080-9 (Original work published 1994)
Francis, P., Flandre, D., Terao, A., & Vandewiele, F. (1994). Modeling of Ultrathin Double-gate Nmos/soi Transistors. IEEE Transactions on Electron Devices, 41(5), 715-720. https://doi.org/10.1109/16.285022 (Original work published 1994)
Flandre, D., & Cristoloveanu, S. (1994). Latch and Hot-electron Gate Current in Accumulation-mode Soi P-mosfets. IEEE Electron Device Letters, 15(5), 157-159. https://doi.org/10.1109/55.291601 (Original work published 1994)
Flandre, D., Jespers, P., Eggermont, JP., & Deceuster, D. (1994). Comparison of Soi Versus Bulk Performance of Cmos Micropower Single-stage Otas. Electronics Letters, 30(23), 1933-1934. https://doi.org/10.1049/el:19941285 (Original work published 1994)
Colinge, J.-P., Flandre, D., & Deceuster, D. (1994). P+-p-p+ Pseudo-bipolar Lateral Soi Transistor. Electronics Letters, 30(18), 1543-1545. https://doi.org/10.1049/el:19941040 (Original work published 1994)
Flandre, D. (1994). Comments on ″Numerical analysis of small-signal characteristics of a fully depleted SOI MOSFET. Solid-State Electronics, 37(7), 1447-1448. https://doi.org/10.1016/0038-1101(94)90205-4 (Original work published 1994)
Deceuster, D., & Flandre, D. (1994). Kink-like Effect in Long N-channel Twin-gate Fully-depleted Soi Mosfets. Electronics Letters, 30(17), 1456-1458. https://doi.org/10.1049/el:19940992 (Original work published 1994)
Francis, P., Flandre, D., Michel, C., & Colinge, J.-P. (1994). Radiation-hard Design for Soi Mos Inverters. IEEE Transactions on Nuclear Science, 41(2), 402-407. https://doi.org/10.1109/23.281534 (Original work published 1994)
Papier de conférence
Francis, P., Terao, A., Flandre, D., & Van de Wiele, F. (1993). Weak inversion models for nMOS Gate-all-Around (GAA) devices. Proceedings of the 23rd European Solid State Device Research Conference, 1993 (ESSDERC ’93), 621-624.
Flandre, D., & Gentinne, B. (1993). Characterization of SOI MOSFETs by gate capacitance measurements. Proceedings of the 1993 International Conference on Microelectronic Test Structures (ICMTS 93) (Cat. No.93CH3220-1), 283-287. https://doi.org/10.1109/ICMTS.1993.292906
Flandre, D. (1993). SOI technology for high-temperature electronics. Proceedings of the 1st European Conference on High Tempeature Electronics, III.
Colinge, J.-P., Flandre, D., & Van de Wiele, F. (1993). Subthreshold slope of accumulation-mode p-channel SOI MOSFETs. Proceedings of the IEEE International SOI Conference, 1993, 146-147. https://doi.org/10.1109/SOI.1993.344558
Gentinne, B., Flandre, D., Colinge, J.-P., & Van de Wiele, F. (1993). High-temperature gate capacitances of thin-film SOI MOSFETs. Proceedings of the 23rd European Solid State Device Research Conference, 1993 (ESSDERC ’93), 687-690.
Flandre, D., Francis, P., Colinge, J.-P., & Cristoloveanu, S. (1993). Comparison of hot-carrier effects in thin-film accumulation-mode SOI and GAA p-MOSFETs. Proceedings of the IEEE International SOI Conference, 1993, 160-161.
Article de journal
Stamatakis, A., Gérard, P., Drochmans, J.-L., Kezai, T., Caby, D., Macq, B., Flandre, D., Luxen, A., Labar, D., Cogneau, M., Robert, A., Heyndrickx, G., & Wijns, W. (1993). Direct comparison of [13N]ammonia and [15O]water estimates of perfusion with quantification of regional myocardial blood flow by microspheres. Circulation, 87(2), 512-525. (Original work published 1993)
Flandre, D. (1993). Analysis of Floating Substrate Effects On the Intrinsic Gate Capacitance of Soi Mosfets Using 2-dimensional Device Simulation. IEEE Transactions on Electron Devices, 40(10), 1789-1796. https://doi.org/10.1109/16.277335 (Original work published 1993)
Rotondaro, ALP., Flandre, D., Magnusson, UK., Claeys, C., Terao, A., & Colinge, J.-P. (1993). Evidence of Different Conduction Mechanisms in Accumulation-mode P-channel Soi Mosfets At Room and Liquid-helium Temperatures. IEEE Transactions on Electron Devices, 40(4), 727-732. https://doi.org/10.1109/16.202784 (Original work published 1993)
Flandre, D., Terao, A., Francis, P., Gentinne, B., & Colinge, JP. (1993). Demonstration of the Potential of Accumulation-mode Mos-transistors On Soi Substrates for High-temperature Operation (150-300-degrees-c). IEEE Electron Device Letters, 14(1), 10-12. https://doi.org/10.1109/55.215084 (Original work published 1993)
Flandre, D., & Gentinne, B. (1993). Extraction of Physical Device Dimensions of Soi Mosfets From Gate Capacitance Measurements. Electronics Letters, 29(7), 586-588. https://doi.org/10.1049/el:19930393 (Original work published 1993)
Auberton-Hervé, A. J., Colinge, J.-P., & Flandre, D. (1993). High-temperature applications of SIMOX technology. Solid State Technology (Japanese Edition), 12-17. (Original work published 1993)
Papier de conférence
Gentinne, B., Flandre, D., Terao, A., & Colinge, J.-P. (1992). Intrinsic gate capacitances and large-signal transient modeling of thin-film accumulation-mode p-channel SOI MOSFETs. Proceedings of the IEEE International SOI Conference, 1992, 52-53. https://doi.org/10.1109/SOI.1992.664790
Francis, P., Terao, A., & Flandre, D. (1992). High temperature characteristics of GAA/SOI transistors and circuits. Proceedings of the IEEE International SOI Conference, 1992, 54-55. https://doi.org/10.1109/SOI.1992.664791
Francis, P., Terao, A., Gentinne, B., Flandre, D., & Colinge, J.-P. (1992). SOI technology for high-temperature applications. Proceedings of the International Electron Devices Meeting, 1992 (IEDM ’92), 353-356. https://doi.org/10.1109/IEDM.1992.307590
Flandre, D. (1992). Recent developments in high-temperature operation of SOI devices and circuits. Communication at the SOI Consortium Meeting. Published. SOI Consortium Meeting, Middlesex University (Angleterre).
Flandre, D., Jacquemin, C., & Colinge, J.-P. (1992). Design techniques for high-speed low-power and high-temperature digital CMOS circuits on SOI. Proceedings of the IEEE International SOI Conference, 1992, 164-165. https://doi.org/10.1109/SOI.1992.664841
Article de journal
Flandre, D., & Terao, A. (1992). Extended Theoretical-analysis of the Steady-state Linear Behavior of Accumulation-mode, Long-channel P-mosfets On Soi Substrates. Solid-State Electronics, 35(8), 1085-1092. https://doi.org/10.1016/0038-1101(92)90009-2 (Original work published 1992)
Flandre, D. (1992). Measurement and Simulation of Floating Substrate Effects On the Intrinsic Gate Capacitance Characteristics of Soi N-mosfets. Electronics Letters, 28(10), 967-969. https://doi.org/10.1049/el:19920614 (Original work published 1992)
Francis, P., Flandre, D., Terao, A., & Vandewiele, F. (1992). Characteristics of Nmos/gaa (gate-all-around) Transistors Near Threshold. Microelectronic Engineering, 19(1-4), 815-818. https://doi.org/10.1016/0167-9317(92)90551-2 (Original work published 1992)
Flandre, D., Terao, A., Loo, T., & Colinge, J.-P. (1992). Physics and Performance of Accumulation-mode Soi P-mosfets From Low (77 K) To High (150-320-degrees-c) Temperatures. Microelectronic Engineering, 19(1-4), 803-806. https://doi.org/10.1016/0167-9317(92)90548-6 (Original work published 1992)
Article de journal
Terao, A., Flandre, D., Loratamayo, E., & Vandewiele, F. (1991). Measurement of Threshold Voltages of Thin-film Accumulation-mode Pmos Soi Transistors. IEEE Electron Device Letters, 12(12), 682-684. https://doi.org/10.1109/55.116954 (Original work published 1991)
Flandre, D., Loo, T., Verlinden, P., & Vandewiele, F. (1991). Interpretation of Quasi-static C-v Characteristics of Mosos Capacitors On Soi Substrates. Electronics Letters, 27(1), 43-44. https://doi.org/10.1049/el:19910028 (Original work published 1991)
Flandre, D., Campabadal, F., Esteve, J., Loratamayo, E., & Vandewiele, F. (1991). Ac Capacitance and Conductance Measurements of 2-terminal Metal-oxide-semiconductor-oxide-semiconductor Capacitors On Silicon-on-insulator Substrates. Journal of Applied Physics, 70(9), 5111-5113. https://doi.org/10.1063/1.350338 (Original work published 1991)
Flandre, D. (1991). Problems in designing thin-film accumulation-mode p-channel SOI MOSFET’s for CMOS digital circuit environment. Electronics Letters, 27(14), 1280-1282 (July 4. https://doi.org/10.1049/el:19910802 (Original work published 1991)
Papier de conférence
Flandre, D., Van de Wiele, F., Jespers, P. G. A., & Haond, M. (1990). Intrinsic gate capacitances of SOI MOSFETs: measurement, modelling, floating substrate effects. In Eccleston, W.; Rosser, P.J.; (ed.), ESSDERC 90. 20th European Solid State Device Research Conference (pp. 437-440). Adam hilger.
Thèse
Flandre, D. (1990). Etude de faisabilité d’une technologie CMOS sur isolant (SOI) dans le domaine des circuits digitaux.
Article de journal
Flandre, D., Vandewiele, F., Jespers, PGA., & Haond, M. (1990). Measurement of Intrinsic Gate Capacitances of Soi Mosfets. IEEE Electron Device Letters, 11(7), 291-293. https://doi.org/10.1109/55.56478 (Original work published 1990)
Papier de conférence
Flandre, D., & Van de Wiele, F. (1989). A physical model for the characterization of SOI MOSFET’s in linear operation. Proceedings of the 19th European Solid State Device Research Conference 1989 (ESSDERC ’89), 755-758.
Flandre, D., & Van de Wiele, F. (1989). Second-order analytical modeling of thin-film SOI MOSFET’s. Proceedings of the 1989 IEEE SOS/SOI Technology Conference, 27-28. https://doi.org/10.1109/SOI.1989.69749
Papier de conférence
Flandre, D., Debleser, M., Vandemeulebroecke, A., & Jespers, P. G. A. (1988). Comparison of equivalent precision dedicated FFT processors. Proceedings of the 1988 IEEE International Symposium on Circuits and Systems (ISCAS 1988)(Cat. No.88CH2458-8), Vol. 2, p. 1919-1922. https://doi.org/10.1109/ISCAS.1988.15313
Terao, A., Paelinck, P., Flandre, D., Verlinden, P., & Van de Wiele, F. (1988). Analytical model for selective laser annealing of SOI. Proceedings of the 1st European SOI Workshop, papier A04.
Terao, A., Paelinck, P., Flandre, D., Verlinden, P., & Van de Wiele, F. (1988). Self-planarization: a new concept for 3-D and high density integrated circuits. Proceedings of the FED 3D Workshop 1988, 165-169.
Flandre, D., Paelinck, P., Terao, A., Verlinden, P., & Jespers, P. (1988). Continuous or discontinuous SOI films : a designer’s point of view. Proceedings of the 1st European SOI Workshop, papier F10.
Article de journal
Paelinck, P., Flandre, D., Terao, A., & Vandewiele, F. (1988). Theoretical-analysis of the 2-terminal Mos Capacitor On Soi Substrate. Journal de Physique, 49(C-4), 67-70. https://doi.org/10.1051/jphyscol:1988413 (Original work published 1988)
Flandre, D., & Vandewiele, F. (1988). A New Analytical Model for the 2-terminal Mos Capacitor On Soi Substrate. IEEE Electron Device Letters, 9(6), 296-299. https://doi.org/10.1109/55.722 (Original work published 1988)
