Seminars
icteam | Louvain-la-Neuve
Scientific seminars are regularly organised by and for ICTEAM researchers in Louvain-la-Neuve. Participation to these seminars is open for anyone interested.
ICTEAM seminars of the week
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[INMA] 2026-09-22 (14:00) : FUTON: Fourier Tensor Network for Implicit Neural Representations
At Euler building (room A.002)
Speaker:
Pooya Ashtari (University of Ghent)
Abstract: Implicit neural representations (INRs) encode signals as continuous functions parameterized by neural networks that map coordinates to values, rather than as grids of discrete samples. Since they are resolution-free, compact, and differentiable with respect to their input coordinates, INRs have become attractive priors for inverse problems involving incomplete or irregularly sampled measurements. INRs are typically implemented as multilayer perceptrons (MLPs) with carefully designed activation functions, but such networks can converge slowly, overfit to noise, and extrapolate poorly.
This talk presents FUTON (Fourier Tensor Network), an INR that represents a signal as a generalized Fourier series with a coefficient tensor factorized using a low-rank decomposition. The two ingredients contribute complementary inductive biases: the orthonormal, separable basis favors smoothness and periodicity, while the low-rank factorization captures the low-dimensional spectral structure of natural signals. The resulting model is shallow and multilinear and requires no learned activation functions. I will show that FUTON is a universal approximator in L²; that evaluating it through an appropriate sequence of tensor contractions reduces an otherwise exponential computational cost to a tractable level; and that it outperforms state-of-the-art MLPs in image and volume representation, trains 2–5× faster, and generalizes better to image super-resolution, denoising, and CT/MRI reconstruction.
[ICTM] 2026-09-22 (11:00) : Ferroelectric Field-Effects with Hafnium Oxide for Neuromorphic Hardware
At Shannon
Speaker:
Laura Bégon-Lours (ETH Zürich)
Abstract: In ferroelectric resistive weights, the strength of the synaptic connection between two neurons is stored in the device conductance. During learning, programming pulses are applied to the synaptic weight, which reconfigures the ferroelectric domains and adjusts the conductance. One strategy to lower the energy cost during the training phase is to lower the duration of the programming pulses. However, the latter cannot be shorter than the self-loading time of the resistive weights, limited by parasitic delays in the circuits. We fabricate ferroelectric resistive weights using bilayers based on hafnia/zirconia superlattices and tungsten oxide. Using this process, CMOS Back-End-Of-Line integration was demonstrated. We determine the maximal device area for which the self-loading time becomes sufficiently short to enable 20 ns programming, which corresponds to a maximum of 3 pJ per pulse. We show that spiking neural network can be deployed on these devices for adaptive electroencephalography decoding. Finaly, ferroelectric capacitors based on the same material also exhibit low-power programming and fast switching speed: full ferroelectric domain reversal is obtained for 5V pulses of only 1 ns.
[ELEN] 2026-09-24 (11:00) : Emerging Memory Integration for Energy-Efficient Edge Computing
At Shannon
Speaker:
Erica Covi (Technical University of Munich )
Abstract: The shift toward edge computing has enabled real-time data processing closer to the source of data collection, reducing latency and improving overall efficiency. Yet this shift imposes strict constraints on power consumption, physical footprint, and computational performance. These constraints cannot be met by conventional hardware approaches alone. At the same time, logic and memory technologies face increasing complexity as continued scaling necessitates consideration of multiple physical processes to sustain device, circuit, and system reliability. This complexity drives the need for Design-Technology-Co-Optimization (DTCO) and System-Technology-Co-Optimization (STCO) approaches, in which systems, circuits, and devices are co-designed to improve performance and address critical development challenges.
Non-volatile memory (NVM) devices show strong potential for enabling energy-efficient, massively parallel computing, owing to their CMOS-compatible operating voltages and analogue behaviour. Incorporating such emerging memory technologies at the back-end-of-line (BEOL) of CMOS circuits or within 3D array configurations opens significant opportunities for next-generation memory and computing systems. Realising this potential, however, requires addressing a set of critical obstacles: device variability, endurance limitations, fabrication compatibility, scalability, adequate compact models supporting circuit design, and system-level integration. These challenges are further compounded as SRAM and embedded DRAM scaling approach fundamental limits, increasing the relevance of Compute-In-Memory approaches and the emerging memory devices that underpin them.
This presentation highlights how DTCO and STCO provide the appropriate framework for navigating this complexity. By co-designing devices, circuits, and architectures in a holistic manner, and exploiting extended regimes of device behaviour, including low-power operation at low voltages, these approaches are of key importance for successfully integrating emerging memory technologies with CMOS circuits, enabling next-generation systems built on BEOL and 3D integration.
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