Electronic Circuits and Systems

Figure : Architecture of a smart sensor node with the related challenges for a sustainable Internet-of-Things

The research direction in electronic circuits and systems at UCL spreads over all levels of abstraction in integrated circuit (IC) design: from nanoscale CMOS process technology to disruptive analog/digital/RF circuit building blocks to complex mixed-signal systems-on-chip (SoCs). An overview of current and latest research activities can be found in this presentation.

Principal Investigators :

David Bol, Denis FlandreJean-Didier Legat, François-Xavier Standaert

Research Areas :

Robust circuit design in emerging CMOS technologies both in More-Moore and More-than-Moore directions require accurate technology characterization and models. In the ECS group, a strong focus is put on analog/RF characterization of these emerging technologies as well as on research in digital design enablement and the study of new concepts related to on-chip sensors, actuators and energy harvesters.

Since 2000, the spectrum of electronic circuits systems is no longer divided into high-performance (high-speed, high accuracy, high robustness, etc.) and low-power applications. Indeed, energy efficiency is today paramount for all types of applications including high-performance computing, wireless communications, remote sensing, harsh-environment operation, power management, etc. In this context, research is carried out in the ECS group to improve the energy efficiency of various types of high-performance applications. Research at the circuit design abstraction level are focused on both analog and digital design methodologies, analog/mixed-signal (AMS) building blocks (RF, power management), digital architecture (DSP, memories) and adaptive techniques, sensing circuits (imagers, biosensors, ADC).

Securing small embedded devices against mathematical and physical attacks while maintaining the level of performances of emerging applications (sensor networks, RFIDs, Internet of Things) is a challenging optimization goal. It usually requires mixing advances at different abstraction levels (protocol, algorithmic, implementation). In this context, we investigate tracks to take advantage of advanced technologies in order to both reduce the implementation and energy cost, and the security of the chip against tampering attacks, fault attacks and side-channel attacks.

The Internet-of-Things (IoT) is progressively changing the way we live but its development triggers key technical challenges. IoT-related researches in the ECS group targets sustainability aspects of the IoT both technical and environmental, energy-harvesting operation (harvesters and power management) and ultra-low-power SoC design with experimental prototyping of SoCs including computing, sensing, wireless communication and power management.

Simulation and design tools are based on industry-standard softwares for integrated processes, devices and circuits. Prototyping is based on both cutting-edge CMOS manufacturing processes from industrial leaders (ST-Microelectronics, TSMC, UMC, X-Fab) and home-brewn processes for functionality diversification (“More than Moore”) supported by UCL WinFab facility. Circuits and systems characterizations are supported by UCL Welcome facility in a very large range of operating conditions (frequencies, temperatures, mechanical stress). Component irradiation for space, biomedical and nuclear physics related investigations is available at the nearby cyclotron research centre on benches qualified by ESA.

The design of custom ICs and SoCs is further investigated in collaboration with experts in the field of application of the circuits (e.g.: image processing, robotics, biomedical, smart sensors, aerospace, radiation hardness, nuclear science, high temperature, energy harvesting, green electronics, ultra low power, RFID, flexible electronics, telecommunication, RF, security, cryptography, etc).

Recent collaborations in electronics circuits and systems include: CEA-LETI (France), ST-Microelectronics (France), CNM (Spain), EADS (France), nSilition (Belgium), CISSOID (Belgium), Deltatec (Belgium), ACIC (Belgium), CETIC (Belgium), IMEC-Holst (Netherlands), AMS (Austria), MGL (Austria), Siemens (Germany), Samsung (UK), Fraunhofer (Germany), Thales (Belgium, France), SOI Industrial Consortium (USA), P.E. International (USA), Purdue University (USA).

Major recent projects (Funding, Topic) include : NanoSec (ARC, security), MSP (FP7, smart building), SAVE (RW, smart buildings/cities), CRASH (ERC, security), STARflo+ (RW, biomedical), TRIADE (FP7, aerospace), E-User (RW, RFID), EUROSOI+ (FP7, low-power SOI), MIMOCOM (RW, MIMO RF systems), S@T (RW, radiation hardness), Trappist (FNRS, nuclear physics), NANOTIC (RW, biochemical wireless sensors).

Most recent publications

Below are listed the 10 most recent journal articles and conference papers produced in this research area. You also can access all publications by following this link : see all publications.

Journal Articles

1. Stoukatch, Serguei; André, Nicolas; Delhaye, Thibault; Dupont, François; Redouté, Jean-Michel; Flandre, Denis. Anisotropic conductive film & flip-chip bonding for low-cost sensor prototyping on rigid & flex PCB. In: IEEE Sensors, Vol. 2020, p. 1-4 (2020). doi:10.1109/SENSORS47125.2020.9278669. http://hdl.handle.net/2078.1/243580

2. Galy, Philippe; Soto, F.; Bourgeat, J.; Jacquier, B.; Kilchytska, Valeriya; Flandre, Denis. Experimental results on diodes and BIMOS ESD devices in 28 nm FD-SOI under TLP & TID radiation. In: Microelectronics Reliability, Vol. 114, p. 113938 (2020). doi:10.1016/j.microrel.2020.113938. http://hdl.handle.net/2078.1/237494

3. Schramme, Maxime; Gimeno Gasca, Cecilia; Cathelin, Andreia; Flandre, Denis; Bol, David. A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI. In: IEEE Solid-State Circuits Letters, Vol. 3, p. 478-481 (2020). doi:10.1109/LSSC.2020.3026759. http://hdl.handle.net/2078.1/235852

4. Wan, Da; Hao, Huang; CHEN, Chen; Abliz, Ablat; Ye, Cong; Liu, Xingqiang; Zou, Xuming; Li, Guoli; Flandre, Denis; Liao, Lei. High Voltage Gain WSe2 Complementary Compact Inverter With Buried Gate for Local Doping. In: IEEE Electron Device Letters, Vol. 41, no.6, p. 944-947 (2020). doi:10.1109/LED.2020.2988488. http://hdl.handle.net/2078.1/229960

5. Gimeno Gasca, Cecilia; Flandre, Denis; Schramme, Maxime; Frenkel, Charlotte; Bol, David. A 2.24-pJ/bit 2.5-Gb/s UWB receiver in 28-nm FDSOI CMOS for low-energy chip-to-chip communications. In: A E Ue: International Journal of Electronics and Communication, Vol. 114, no. 152996, p. 8 (2020). doi:10.1016/j.aeue.2019.152996. http://hdl.handle.net/2078.1/223380

6. Kovačič, M.; Krč, J.; Lipovšek, B.; Chen, W-C.; Edoff, M.; Bolt, P.J.; van Deelen, J.; Zhukova, Maria; Lontchi Jioleo, Jackson; Flandre, Denis; Salomé, P.; Topič, M. Modelling Supported Design of Light Management Structures in Ultra-Thin Cigs Photovoltaic Devices. In: Informacije MIDEM : journal of microelectronics, electric components and materials, Vol. 49, no.3, p. 183-190 (2019). doi:10.33180/InfMIDEM2019.307. http://hdl.handle.net/2078.1/226845

7. Frenkel, Charlotte; Legat, Jean-Didier; Bol, David. MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. In: IEEE Transactions on Biomedical Circuits and Systems, Vol. 13, no.5, p. 999-1010 (2019). doi:10.1109/TBCAS.2019.2928793. http://hdl.handle.net/2078.1/226234

8. Frenkel, Charlotte; Lefebvre, Martin; Legat, Jean-Didier; Bol, David. A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS. In: IEEE Transactions on Biomedical Circuits and Systems, Vol. 13, no.1, p. 145-158 (2019). doi:10.1109/TBCAS.2018.2880425. http://hdl.handle.net/2078.1/214668

9. Gimeno Gasca, Cecilia; Flandre, Denis; Bol, David. Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis. In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, Vol. 65, no.6, p. 2015-2023 (2018). doi:10.1109/TCSI.2017.2765312. http://hdl.handle.net/2078.1/211253

10. Gimeno Gasca, Cecilia; Bol, David; Flandre, Denis. Multilevel Half-Rate Detector for Clock and Data Recovery Circuits. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , p. 5 (2018). doi:10.1109/TVLSI.2018.2826440. http://hdl.handle.net/2078.1/199147

Conference Papers

1. Wei, Peng; André, Nicolas; Zeng, Xi; Sabri Alirezaei, Iman; Li, Guoli; Bouterfa, Mohamed; Francis, Laurent; Flandre, Denis. Micrometer-thin SOI Sensors for E-Skin Applications. In: IEEE Sensors. Proceedings. I E E E, 2020 xxx. doi:10.1109/SENSORS47125.2020.9278716. http://hdl.handle.net/2078.1/243039

2. Frenkel, Charlotte; Legat, Jean-Didier; Bol, David. A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. In: Proceedings of ISCAS 2020. p. 5. IEEE, 2020 xxx. doi:10.1109/ISCAS45731.2020.9180440. http://hdl.handle.net/2078.1/236441

3. Flandre, Denis; Schramme, Maxime; Gimeno Gasca, Cecilia; Drouguet, Maxime; André, Nicolas; Craeye, Christophe; Bol, David. Cinq générations de chips UWB (Ultra-Wide-Band) pour la géo-localisation et la transmission de données à très basse consommation. 2020 xxx. http://hdl.handle.net/2078.1/227585

4. Martins d’Oliveira, Ligia; Kilchytska, Valeriya; Flandre, Denis; de Souza, Michelly. Harmonic Distortion in Symmetric and Asymmetric Self-Cascodes of UTBB FD SOI Planar MOSFETs. 2019 xxx. http://hdl.handle.net/2078.1/227417

5. Martínez-Pérez, Antonio D.; Gimeno Gasca, Cecilia; Flandre, Denis; Aznar, Francisco; Royo, Guillermo; Sánchez-Azqueta, Carlos. Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA. In: Proceedings of SMACD 2019, IEEE, 2019 xxx. doi:10.1109/SMACD. http://hdl.handle.net/2078.1/218945

6. Bol, David; Schramme, Maxime; Moreau, Ludovic; Haine, Thomas; Xu, Pengcheng; Frenkel, Charlotte; Dekimpe, Rémi; Stas, François; Flandre, Denis. A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode. In: Proceedings of the 2019 IEEE International Solid- State Circuits Conference (ISSCC 2019), IEEE, 2019, 978-1-5386-8531-0/19, 322-323 xxx. doi:10.1109/ISSCC.2019.8662293. http://hdl.handle.net/2078.1/214779

7. Dekimpe, Rémi; Xu, Pengcheng; Schramme, Maxime; Flandre, Denis; Bol, David. A Battery-less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer. 2018 xxx. http://hdl.handle.net/2078.1/214781

8. Xu, Pengcheng; Flandre, Denis; Bol, David. Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors. In: Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018, 107-110 xxx. http://hdl.handle.net/2078.1/209319

9. Haine, Thomas; Flandre, Denis; Bol, David. An 8-T ULV SRAM macro in 28nm FDSOI with 7.4 pW/bit retention power and back-biased-scalable speed/energy trade-off. 2018 xxx. http://hdl.handle.net/2078.1/207942

10. Gimeno Gasca, Cecilia; Flandre, Denis; Bol, David. Low-Power Half-Rate Dual-Loop Clock-Recovery System in 28-nm FDSOI. 2018 xxx. http://hdl.handle.net/2078.1/196445